Yunsup Lee
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702ddabe26
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add ExampleSmallConfig for README
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2014-10-07 02:07:59 -07:00 |
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Yunsup Lee
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e25d420155
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Improve ChiselConfig composability; bump chisel
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2014-10-06 13:43:40 -07:00 |
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Yunsup Lee
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73eac94a65
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Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
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2014-10-06 13:40:35 -07:00 |
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Henry Cook
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122733b3a9
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file name consistency
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2014-10-06 13:37:38 -07:00 |
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Henry Cook
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0b5f23a209
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Streamlined uncore for release
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2014-10-06 13:37:15 -07:00 |
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Adam Izraelevitz
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15fb4730ec
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Add BuildTile parameter for Tile
Conflicts:
rocket
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2014-09-25 06:50:45 -07:00 |
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Henry Cook
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7398b00d93
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dir supplied by function
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2014-09-25 06:50:41 -07:00 |
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Henry Cook
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5a840c5520
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support for multiple tilelink paramerterizations in same design
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2014-09-25 06:50:30 -07:00 |
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Donggyu Kim
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eb384f6461
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new RocketChipBackend implementation
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2014-09-25 06:47:12 -07:00 |
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Scott Beamer
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f2ca887de3
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better fpga configs
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2014-09-25 06:47:03 -07:00 |
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Donggyu Kim
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4fe48f5a0a
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bump chisel
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2014-09-25 06:46:58 -07:00 |
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Donggyu Kim
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60d90f5230
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recover collectNodesIntoComp in Backends.scala
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2014-09-25 06:46:50 -07:00 |
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Donggyu Kim
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a53091b40f
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remove collectNodesIntoComp from Backends.scala
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2014-09-25 06:46:27 -07:00 |
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Scott Beamer
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f4e6cd75ab
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turn off fpu for default fpga config.
a larger fpga can use defaultconfig
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2014-09-25 06:46:16 -07:00 |
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Yunsup Lee
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09de2e2794
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compute number of outstanding misses for DRAMSideLLCNull
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2014-09-12 18:09:38 -07:00 |
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Yunsup Lee
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1cfd9f5a0e
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add LICENSE
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2014-09-12 10:15:04 -07:00 |
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Yunsup Lee
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c98afa1fea
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turn off DRAMSideLLC
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2014-09-11 22:10:25 -07:00 |
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Yunsup Lee
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b5a64487eb
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turn off DRAMSideLLC
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2014-09-11 22:07:44 -07:00 |
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Yunsup Lee
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02c08a156f
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generate consts.vh from chisel source
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2014-09-10 17:14:55 -07:00 |
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Yunsup Lee
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6b6bdd2b83
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decommission Slave top-level module for fpga build
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2014-09-08 00:23:15 -07:00 |
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Yunsup Lee
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ddfd3ce968
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further generalize fpga/vlsi builds
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2014-09-08 00:21:57 -07:00 |
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Henry Cook
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ae05125f29
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Adjustements to top-level parameters and knobs for hwacha
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2014-09-07 17:57:33 -07:00 |
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Henry Cook
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4126678c9d
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Merge branch 'dse'
Conflicts:
rocket
uncore
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2014-09-06 06:59:14 -07:00 |
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Henry Cook
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82467313dd
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merge in rocketchip changes from master
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2014-09-02 13:51:57 -07:00 |
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Yunsup Lee
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7734285507
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forgot to comment out hwacha
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2014-09-01 09:01:36 -07:00 |
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Yunsup Lee
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c03c09ec31
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update for rocket-chip release
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2014-08-31 20:26:55 -07:00 |
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Henry Cook
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78ab83d224
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refactor fpga top/config
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2014-08-28 13:07:54 -07:00 |
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Henry Cook
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bf356b9cb4
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Refactor to combine fpga and vlsi tops, part 1
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2014-08-24 19:30:53 -07:00 |
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Henry Cook
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a41d55b643
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Final parameter refactor.
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2014-08-23 01:26:03 -07:00 |
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Scott Beamer
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63b62394d9
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added l2 to fpga
with new chisel & uncore, it goes into brams
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2014-08-20 15:41:07 -07:00 |
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Henry Cook
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1563c1bb36
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Fixed cache params. Asm and bmark tests pass.
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2014-08-12 15:00:54 -07:00 |
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Henry Cook
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7f07771600
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Cache utility traits. Completely compiles, asm tests hang.
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2014-08-11 18:37:10 -07:00 |
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Henry Cook
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1983260e6f
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a few more fixes. some param lookups fail (here() in Alter blocks)
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2014-08-10 23:08:21 -07:00 |
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Henry Cook
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63bd0b9d2a
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Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
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2014-08-08 12:27:47 -07:00 |
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Adam Izraelevitz
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08d81d0892
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First cut at using new chisel parameters for toplevel parameters and fpu
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2014-08-01 18:09:37 -07:00 |
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Henry Cook
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434da22283
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Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel)
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2014-05-28 17:16:49 -07:00 |
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Henry Cook
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b0ccb88982
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make outer cache type choice a top-level const
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2014-05-28 14:46:07 -07:00 |
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Henry Cook
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ce056b4b89
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client/master -> inner/outer
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2014-04-29 16:50:30 -07:00 |
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Henry Cook
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224e286dd3
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New uncore config objects. Backends get their own file. Simplify fpga uncore.
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2014-04-26 19:46:11 -07:00 |
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Henry Cook
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3d4273954a
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TileLinkIO.GrantAck -> TileLinkIO.Finish
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2014-04-26 15:19:25 -07:00 |
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Henry Cook
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fbf6e44376
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fix connection error in fpga uncore
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2014-04-24 11:58:59 -07:00 |
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Henry Cook
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cfd6748318
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patches to make FAME1/dram IOs compile with up-to-date chisel (bumped)
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2014-04-21 17:26:33 -07:00 |
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Henry Cook
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2cb4dbae39
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Refactored uncore constants and tilelink data
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2014-04-10 13:19:50 -07:00 |
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Henry Cook
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5a5f69bfca
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finished uncore constant/tilelink data refactor
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2014-04-10 13:13:46 -07:00 |
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Andrew Waterman
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817517c663
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Better branch prediction
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2014-04-07 16:08:06 -07:00 |
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Henry Cook
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56f515c255
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first steps in uncore constant/tilelink data refactor
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2014-03-30 09:21:08 -07:00 |
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Andrew Waterman
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d055c0ebaf
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Push rocket/hardfloat/chisel
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2014-03-04 16:39:06 -08:00 |
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Yunsup Lee
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e20d50436a
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committed in the wrong directory, meant to commit in the hwacha directory
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2014-03-01 00:01:35 -08:00 |
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Yunsup Lee
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8c459df3b6
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flush deck when xcpt occurs, fixes remaining p test bugs
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2014-02-28 22:50:34 -08:00 |
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Stephen Twigg
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755293d785
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Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha).
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2014-02-14 10:12:09 -08:00 |
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