Megan Wachs
8163a6b597
Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications
2016-09-02 11:11:40 -07:00
Andrew Waterman
c05ba1e864
Add TileId parameter, generalizing GroundTestId
...
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
2016-09-02 00:10:50 -07:00
Yunsup Lee
4a7972be31
connect testharness components via member functions ( #236 )
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to prevent code duplication for new testbenches
2016-09-01 18:38:39 -07:00
Howard Mao
08089f695d
allow configuration to be in separate project from test harness
2016-09-01 10:28:07 -07:00
Howard Mao
c66318307c
no longer need to set invalidate_lr in RoCC examples
2016-08-31 22:05:35 -07:00
Howard Mao
27c674972c
tie off invalidate_lr in RoCC
2016-08-31 22:00:27 -07:00
Howard Mao
bb578494d8
don't override req.bits.phys in SimpleHellaCacheIF
2016-08-31 22:00:27 -07:00
Howard Mao
50d6738caf
make sure DummyPTW sets all the necessary status and ptbr signals
2016-08-31 22:00:27 -07:00
Howard Mao
403cc1c5c4
fix DecoupledTLB to handle misses appropriately
2016-08-31 22:00:27 -07:00
Andrew Waterman
f4524e4c91
Add PML for Boolean.option; use it
2016-08-31 13:43:04 -07:00
Andrew Waterman
2dfcf18167
Filter simv command-line args starting with -cm
...
These confuse HTIF, so don't pass them through.
Contributed by @scottj97.
2016-08-31 13:39:35 -07:00
Howard Mao
cf1bd90a70
Merge pull request #234 from zizztux/fix_export_mmio
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Add address map entries for exported mmio port.
2016-08-30 15:58:01 -07:00
SeungRyeol Lee
b1ce3b8c98
Add address map entries for exported mmio port.
2016-08-31 06:58:38 +09:00
Andrew Waterman
8dbee2b133
Don't conditionalize running bmarks on UseVM
2016-08-29 13:43:29 -07:00
Andrew Waterman
07d48df88a
Get rid of FPU RoCC port logic when RoCC not present
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The previous approach used ex_reg_valid to determine whether to
source data from the FPU or RoCC. Thus, when the RoCC was not
present, it was still creating muxes. Using ex_cp_valid instead
gets rid of them.
2016-08-29 12:59:17 -07:00
Andrew Waterman
f91552a650
Add performance counter support
2016-08-29 12:31:52 -07:00
Andrew Waterman
1e3339e97c
Update breakpoints to match @timsifive's debug spec
2016-08-29 12:31:52 -07:00
Andrew Waterman
9ca82dd397
reset default MulDiv config to moderately fast default
...
Closes #228 .
In commit 3f8c60bbd6
2016-08-29 12:31:52 -07:00
Andrew Waterman
33eaf08b60
set missing port direction
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Ideally, chisel should flag this as an error.
2016-08-29 12:31:52 -07:00
Howard Mao
a19bd6de96
Get in line with FIRRTL randomization flag changes ( #231 )
2016-08-29 12:29:01 -07:00
mwachs5
35948918b6
Merge pull request #226 from ucb-bar/coreplex_peripheral_interrupts
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Allow some External Interrupts to come from Periphery
2016-08-26 11:52:04 -07:00
Megan Wachs
53ee54dbd1
Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself
2016-08-26 10:40:39 -07:00
Megan Wachs
41aa80c5d7
Merge remote-tracking branch 'origin/master' into coreplex_peripheral_interrupts
2016-08-26 09:32:36 -07:00
Ben Keller
79293f4fa2
Use a better iterator inside the DCache
2016-08-25 20:41:39 -07:00
Henry Cook
115e8edd83
Merge branch 'master' into coreplex_peripheral_interrupts
2016-08-25 17:26:56 -07:00
Henry Cook
93c801f598
Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. ( #227 )
2016-08-25 17:26:28 -07:00
Henry Cook
abfaae8f4b
Merge branch 'master' into coreplex_peripheral_interrupts
2016-08-25 14:57:53 -07:00
Ben Keller
4f388add67
More accurate conditional include of generated .d make fragment ( #222 )
2016-08-25 14:42:04 -07:00
Megan Wachs
428eed79a1
Allow some External Interrupts to come from Periphery
2016-08-25 14:16:33 -07:00
mwachs5
8ff739d3fa
Merge pull request #225 from ucb-bar/remove-openocd
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Remove openocd from .gitmodules
2016-08-25 11:01:17 -07:00
Megan Wachs
3a674b413d
Remove openocd from .gitmodules
2016-08-25 10:05:30 -07:00
mwachs5
d5d076200e
Merge pull request #213 from ucb-bar/new_test_jtag_DTM
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Adds Logic & test support for JTAG implementation of Debug Transport Module.
2016-08-23 18:18:18 -07:00
Megan Wachs
67467c65f5
Add a jtag-dtm-regression target to the regression
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This doesn't get added to Travis, but this target can be used
by other automated testing tools which may want to do further
testing on rocket-chip.
2016-08-23 16:53:50 -07:00
Megan Wachs
32118269c1
Remove } introduced in merge
2016-08-23 08:20:52 -07:00
Megan Wachs
c22c77c7a4
remove pointer to openOCD
2016-08-23 07:35:48 -07:00
Megan Wachs
9974626d6a
Merge remote-tracking branch 'origin/master' into HEAD
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Conflicts:
src/main/scala/rocketchip/TestHarness.scala
2016-08-23 07:34:01 -07:00
Howard Mao
61aa716f44
fix bus axi connections in periphery
2016-08-22 11:57:15 -07:00
Howard Mao
f9ea14b4c2
extra devices should get elaborated in a single build function
2016-08-22 11:57:15 -07:00
Scott Johnson
96e2cefb34
Merge branch 'master' into HEAD
2016-08-22 11:37:30 -07:00
Scott Johnson
8d6f080ed0
Merge pull request #215 from ucb-bar/test-harness-fixes
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Test harness fixes
2016-08-22 10:33:01 -07:00
Andrew Waterman
b7181ba49b
Merge branch 'master' into test-harness-fixes
2016-08-19 22:53:12 -07:00
mwachs5
22ffe36258
Add a queue for timing QoR between L2->MMIO network ( #217 )
2016-08-19 22:51:49 -07:00
Scott Johnson
96a868d388
enable the TestDriver to be used in a SystemVerilog UVM-based testbench, which has its own way to manage end-of-simulation and does not like anyone else to call $finish
2016-08-19 17:14:54 -07:00
Scott Johnson
2d12f6689c
make CLOCK_PERIOD actually be the clock period, instead of half of the clock period
2016-08-19 16:55:57 -07:00
Scott Johnson
4dbcc568dc
reorder code to get rid of messy -1
2016-08-19 16:55:57 -07:00
Scott Johnson
f945acf712
rm race condition on trace_count
2016-08-19 16:55:57 -07:00
Megan Wachs
75efc7dee7
JtagIO's DRV_TDO should be an INPUT
2016-08-19 16:38:03 -07:00
Megan Wachs
723cc063cb
Move files after the file reorganization
2016-08-19 16:11:41 -07:00
Megan Wachs
48c5ec3551
add missing jtag file
2016-08-19 16:08:32 -07:00
Megan Wachs
66a253a0db
Remove unncessary file
2016-08-19 16:08:31 -07:00
