riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
1,030 Commits 1 Branch 0 Tags 13 MiB
adb7eacf6e
Commit Graph

1021 Commits

Author SHA1 Message Date
Andrew Waterman
6d1bf5c014 Use generic LoadGen/StoreGen 2015-11-24 18:13:33 -08:00
Sagar Karandikar
65632c875a Merge branch 'master' into rocc-fpu-port 2015-11-21 02:24:38 -08:00
Howard Mao
b0a06a77db fix a few Chisel3 compat issues 2015-11-20 13:33:15 -08:00
Yunsup Lee
94d2dd3053 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-16 23:29:25 -08:00
Andrew Waterman
0f092b9b59 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:51:43 -08:00
Yunsup Lee
5e2698adbc Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-14 16:44:55 -08:00
Yunsup Lee
213c1a4c81 fix fdiv/fsqrt control bug in fpu 2015-11-14 16:43:15 -08:00
Yunsup Lee
4dd097d156 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-14 14:52:13 -08:00
Yunsup Lee
3c3c946755 move to new version of hardfloat 2015-11-14 14:49:17 -08:00
Yunsup Lee
608e4b2851 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-12 20:44:25 -08:00
Howard Mao
19daee10f0 use default constructors for IOMSHR acquire construction 2015-11-12 15:54:05 -08:00
jackkoenig
1e259a55da Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later 2015-11-08 21:16:31 -08:00
Yunsup Lee
df5daaa72e Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-11-06 23:57:42 -08:00
Andrew Waterman
2f515b2af6 Reduce critical path for fdiv valid signal 2015-11-06 23:28:31 -08:00
Colin Schmidt
86d67051b2 Merge commit 'e31be75' into rocc-fpu-port 2015-10-26 16:29:51 -07:00
Yunsup Lee
c7235fecb5 further state optimization in CSRfile when not UseVM 2015-10-25 10:23:46 -07:00
Colin Schmidt
652fb393a3 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-10-22 16:38:28 -07:00
Jim Lawson
0c587704a7 Add ability to generate libraryDependency on cde. 2015-10-22 11:37:20 -07:00
Henry Cook
4f8468b60f depend on external cde library 2015-10-21 18:19:23 -07:00
Colin Schmidt
942f6a7d7f Merge commit 'd1eae61970f864afe4fde8ca7f75380c70c4658f' into rocc-fpu-port 2015-10-21 17:18:20 -07:00
Colin Schmidt
97f29b1618 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-10-21 11:33:42 -07:00
Howard Mao
0b7c828b5d go back to using standard LockingArbiter 2015-10-21 09:15:51 -07:00
Howard Mao
c68d9f8137 make ProbeUnit state machine easier to understand 2015-10-20 23:25:23 -07:00
Henry Cook
1a1185be3f Vectorize ROCC and Tile memory interfaces 2015-10-20 15:02:24 -07:00
Colin Schmidt
2cee8c8bec Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port 2015-10-18 13:09:17 -07:00
Henry Cook
6f8997bee9 Minor refactor of StoreGen/AMOALU. 2015-10-16 19:12:46 -07:00
Henry Cook
1441590c3b add enabled field to BTBParameters 2015-10-16 19:12:39 -07:00
Henry Cook
969ecaecf8 pass parameters to BuildRoCC 2015-10-14 14:16:47 -07:00
Henry Cook
68cb54bc68 refactor tilelink params 2015-10-14 12:14:36 -07:00
Henry Cook
4508666d96 log2ceil 2015-10-06 18:22:47 -07:00
Henry Cook
8173695800 added HasAddrMapParameters 2015-10-06 18:22:40 -07:00
Henry Cook
84576650b5 Removed all traces of params 2015-10-05 21:48:05 -07:00
Henry Cook
69a4dd0a79 refactor NASTI to not use param 2015-10-02 14:20:47 -07:00
Howard Mao
19656e4abe make sure to generate release from clean coh state on probe miss 2015-09-30 16:58:18 -07:00
Andrew Waterman
833909a2b5 Chisel3 compatibility fixes 2015-09-30 14:36:26 -07:00
Andrew Waterman
a7c908cb83 Don't declare Reg inside of when 
We haven't yet decided what the Chisel3 semantics for this will be.
 2015-09-30 12:43:36 -07:00
Howard Mao
2f3d15675c fix DataArray writemask in L1D 2015-09-28 16:02:39 -07:00
Andrew Waterman
f8a7a80644 Make perf counters optional 2015-09-28 13:55:23 -07:00
Andrew Waterman
5e88ead984 Add pseudo-ops to instructions.scala 2015-09-28 11:52:27 -07:00
Andrew Waterman
b93a94597c Remove needless control logic 2015-09-27 13:31:52 -07:00
Howard Mao
4bda6b6757 fix bug in tlb refill 2015-09-26 21:27:36 -07:00
Howard Mao
6bf8f41cef make sure passthrough requests are treated as vm_enabled = false 2015-09-26 20:29:51 -07:00
Andrew Waterman
c3fff12ff0 Revert "replace remaining uses of Vec.fill" 
This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
 2015-09-25 17:09:06 -07:00
Andrew Waterman
0bfb2962a6 Assume coh.isRead returns true for store-conditional 
This requires an uncore update.
 2015-09-25 15:26:11 -07:00
Howard Mao
a66bdb1956 replace remaining uses of Vec.fill 2015-09-24 17:53:26 -07:00
Howard Mao
9eb988a4c6 make sure access to invalid physical address treated as exception 2015-09-22 10:11:43 -07:00
Howard Mao
16c748576a don't mux data_word_bypass between IOMSHR and cache 2015-09-22 10:10:57 -07:00
Howard Mao
d89bcd3922 modify csr file to bring in line with HTIF changes 2015-09-22 10:10:57 -07:00
Howard Mao
382faba4a6 Implement bypassing L1 data cache for MMIO 2015-09-22 10:10:57 -07:00
Andrew Waterman
e72e5a34b5 Fix storage of SP values in DP registers 
The SFMA was zero-extending the SP value to 65 bits, rather than filling
the upper 32 bits with 1s.  This meant that an FSD + FLD of that register
would not restore the value properly.

Also, minor code cleanup.
 2015-09-21 12:20:44 -07:00
Christopher Celio
76bf1da310 [commitlog] zero-extend SP write-back values 2015-09-15 16:47:26 -07:00
Scott Beamer
3b48d8569c [commitlog] don't print out writebacks to x0 2015-09-15 16:47:26 -07:00
Christopher Celio
e22bf02a80 [commitlog] CSR's cycle optionally set to instret 
- Allows debugging Rocket against Spike by having timer interrupts
    occur in the same place in the instruction stream for both.
 2015-09-15 16:47:26 -07:00
Christopher Celio
7d14abf262 [commitlog] Added privilege-level to output 2015-09-15 16:47:24 -07:00
Christopher Celio
53a02a62c8 [commitlog] Fix sp/dp bug in FPU writeback 2015-09-15 16:46:47 -07:00
Christopher Celio
d630a03857 [commitlog] Added FP instructions to the commitlog 2015-09-15 15:59:13 -07:00
Christopher Celio
91458bef1c [commitlog] Initial commit log for integer working 2015-09-15 15:59:03 -07:00
Andrew Waterman
78b2e947de Chisel3 compatibility fixes 2015-09-11 15:43:07 -07:00
Colin Schmidt
d292b6cb13 don't connect rocc-fpu-port without rocc accel 2015-09-08 14:44:12 -07:00
Albert Ou
3d6a060dc3 Bump Scala to 2.11.6 
This change, originally part of commit b978083, was excluded from the
merge at commit 47494ec.
 2015-08-10 23:52:58 -07:00
Colin Schmidt
cab12635f8 Merge master into rocc-fpu-port 
ebb33f2f4b658211960a4c6c023c139420c67212
 2015-08-06 08:03:10 -07:00
Andrew Waterman
1718333f83 Don't use Vec as lvalue 2015-08-05 15:29:33 -07:00
Andrew Waterman
546205b174 Chisel3 compatibility: use >>Int instead of >>UInt 2015-08-05 15:29:03 -07:00
Andrew Waterman
fb5524372d bump scala to 2.11.6 2015-08-03 19:51:08 -07:00
Andrew Waterman
d4c94c6566 Chisel3 has different Vec semantics 
Vec(a, b) := c doesn't modify a and b in chisel3.
 2015-08-03 19:08:00 -07:00
Andrew Waterman
c345d72af4 Chisel3: Flip order of := and <> 2015-08-03 18:53:09 -07:00
Andrew Waterman
ef319edc84 Bits -> UInt 2015-08-02 21:03:42 -07:00
Andrew Waterman
52fc34a138 Chisel3: bulk connect is not commutative 
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
 2015-08-01 21:11:25 -07:00
Andrew Waterman
6c0e1e33ab Purge UInt := SInt assignments 2015-07-31 15:42:10 -07:00
Andrew Waterman
6d7cc37e87 Specify some uninferrable widths 
It's really scary that Chisel2 passed this stuff.
 2015-07-31 14:23:52 -07:00
Andrew Waterman
45cf64dbd7 Use UInt instead of Vec[Bool] 2015-07-31 04:59:45 -07:00
Andrew Waterman
57930e8a26 Chisel3 compatibility potpourri 2015-07-30 23:53:02 -07:00
Jim Lawson
db7258f887 Add junctions to the possible managed dependency list. 2015-07-30 15:11:23 -07:00
Henry Cook
d2a594fb57 new junctions repo has mem size constants 2015-07-29 18:05:54 -07:00
Henry Cook
9d67ef4ee2 simplify .sbt files 2015-07-29 17:22:33 -07:00
Andrew Waterman
ce161b83e3 Chisel3 compatibility: avoid subword assignment 2015-07-29 15:03:13 -07:00
Andrew Waterman
c8c312e860 minor btb cleanup 2015-07-29 15:03:01 -07:00
Andrew Waterman
a2fdcdcaef Use Seq, not Iterable, when traversal order matters 2015-07-29 00:24:58 -07:00
Andrew Waterman
431dd2219b Another Bits -> BitPat 2015-07-28 20:13:56 -07:00
Andrew Waterman
049fc8dc24 Chisel3 compatibility: use BitPat for don't-cares 
This one's hella ugly, but for the time being, idgaf.
 2015-07-28 02:48:49 -07:00
Andrew Waterman
f2dcc40e67 Chisel3 compatibility changes 2015-07-27 12:42:20 -07:00
Andrew Waterman
ae73e3a997 Only instantiate div/sqrt unit if requested 2015-07-22 22:18:18 -07:00
Andrew Waterman
e9433ee01e Minor cleanup 2015-07-22 17:38:08 -07:00
Andrew Waterman
b4e4ceed3d Factor out some more hazard detection code 2015-07-22 15:52:13 -07:00
Andrew Waterman
bd785e7d19 Factor out common hazard detection code 2015-07-22 15:46:20 -07:00
Andrew Waterman
cc447c8110 Refactor pipeline RTL (merge ctrl + dpath into rocket) 2015-07-21 17:10:56 -07:00
Andrew Waterman
ac6e73e317 Add Wire() wrap 2015-07-15 20:24:18 -07:00
Andrew Waterman
5b7f3c3006 Don't use clone 2015-07-15 17:30:50 -07:00
Henry Cook
f5b3649b73 Merge commit 'd819fb28c3370747475d7c5f4b641723cab1fd0c' into rocc-fpu-port 2015-07-15 15:29:56 -07:00
Andrew Waterman
be2ff6dec7 Vec(Reg) -> Reg(Vec) 2015-07-15 12:33:46 -07:00
Andrew Waterman
a78e28523c Chisel3: Don't mix Mux types 2015-07-11 14:06:08 -07:00
Andrew Waterman
3233867390 Use Chisel3 SeqMem construct 2015-07-11 13:34:57 -07:00
Henry Cook
5ed2899e56 Merge pull request #10 from wsong83/fix 
L1 D$ writeback unit, reduce re-read data array
 2015-07-06 15:18:49 -07:00
Andrew Waterman
5362e2bbbd New machine-mode timer facility 2015-07-05 16:38:49 -07:00
Andrew Waterman
5e009ecc75 Fix an apparently benign PC sign-extension bug 2015-06-11 16:08:39 -07:00
Colin Schmidt
4b6cd7f3eb Merge branch 'master' of ucb-bar/rocket into rocc-fpu-port for priv1.7 2015-06-03 15:51:53 -07:00
Wei Song
4db60d9e9d code clean in dcache, no need to check the condition twice. 2015-06-02 22:06:12 +01:00
Wei Song
b6e68773fd nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array. 2015-05-30 16:25:27 +01:00
Andrew Waterman
6a9390c50e Avoid spurious D$ assertion failures 
For the Rocket pipeline, this fix is needless and the problem is that the
assertion is too conservative, but I solved it this way to avoid problems
for other plausible use cases where physical and virtual accesses are
intermixed.
 2015-05-19 03:00:53 -07:00
Andrew Waterman
f460cb6c54 Update to privileged architecture 1.7 2015-05-19 02:32:21 -07:00