Andrew Waterman
a21979a2fa
Bits -> UInt
2015-08-03 18:01:06 -07:00
Andrew Waterman
9c7a41e8d3
Chisel3: bulk connect is not commutative
...
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:09:00 -07:00
Andrew Waterman
6fc807f069
Chisel3: Avoid subword assignment
2015-08-01 21:08:35 -07:00
Andrew Waterman
6d574f8c1b
Fix incompatible assignment
2015-07-31 00:59:34 -07:00
Andrew Waterman
377e17e811
Add Wire() wrap
2015-07-31 00:32:02 -07:00
Andrew Waterman
0686bdbe28
Avoid cross-module references
...
You can't instantiate a Vec in one module and use it in another.
An idiosyncrasy of the Chisel2 implementation let this one slip by.
In this case, it's just a matter of using def instead of val.
2015-07-30 23:49:06 -07:00
Andrew Waterman
8f7b390353
UInt-> Bits; avoid mixed UInt/SInt code
2015-07-30 23:49:06 -07:00
Andrew Waterman
6c391e3b37
Use UInt(0), not UInt(width=0), for constant 0
2015-07-30 23:49:06 -07:00
Andrew Waterman
a69c749249
Fix compilation with scala 2.11.6
...
We forgot to specify return types on overloaded methods, and a previous
version of the scala compiler failed to flag this as an error.
2015-07-28 16:24:45 -07:00
Andrew Waterman
f8ec6d6393
Chisel3 compatibility: use BitPat for don't-cares
...
Also, call the UInt factory instead of the Bits one, for good measure.
2015-07-28 02:46:23 -07:00
Andrew Waterman
0e06c941df
Chisel3 compatibility fixes
2015-07-23 14:58:46 -07:00
Andrew Waterman
3c0475e08b
Add Wire() wrap
2015-07-15 20:24:03 -07:00
Andrew Waterman
2d6b3b2331
Don't use clone
2015-07-15 18:06:27 -07:00
Andrew Waterman
276f53b652
Delete BigMem; it's not used anymore
2015-07-15 17:41:47 -07:00
Andrew Waterman
15cec0eab7
Vec(Reg) -> Reg(Vec)
2015-07-15 12:44:54 -07:00
Andrew Waterman
e76a9d3493
Chisel3: Don't mix Mux types
2015-07-11 14:05:39 -07:00
Andrew Waterman
5dc3da008e
Use Chisel3 SeqMem construct
2015-07-11 13:36:26 -07:00
Andrew Waterman
55059632c4
Temporarily use HTIF to push RTC value to cores
2015-07-05 16:19:39 -07:00
Andrew Waterman
b4e38192a1
Fix (?) L2$ miss bug
...
The victim's metadata was incorrectly used for the new line.
2015-06-24 18:01:56 -07:00
Andrew Waterman
ea76800d1a
Fix data array reset bug
...
io.resp.valid could have been valid the cycle after reset, causing the
write mask in the acquire tracker to have an erroneous value after reset.
This caused the L1 I$ to be refilled with the wrong data.
This probably only affects programs loaded with +loadmem and so shouldn't
matter for the EOS24 silicon. It should only affect the first L2 xact,
which, in practice, would be an HTIF write to load the program.
2015-06-11 15:28:23 -07:00
Andrew Waterman
c941f0a68e
New virtual memory implementation (Sv39)
2015-03-27 16:21:29 -07:00
Andrew Waterman
6e540825b2
Use entire 12-bit CSR address
2015-03-14 02:15:24 -07:00
Andrew Waterman
d04da83f96
Make data RAMs 1RW instead of 1R1W
2014-12-15 17:36:17 -08:00
Andrew Waterman
9bf10ae5d2
remove extraneous toBits (need new Chisel)
2013-09-19 15:26:36 -07:00
Andrew Waterman
cc7783404d
Add memory command M_XA_XOR
2013-09-12 16:09:53 -07:00
Andrew Waterman
0672773c1a
for now, don't use asserts outside of components
2013-05-09 02:14:44 -07:00
Andrew Waterman
7ff5b5b86f
treat load-reserved as a non-dirtying store
2013-04-07 19:25:26 -07:00
Andrew Waterman
3479f1c6cd
add LR/SC support
2013-04-07 19:25:20 -07:00
Andrew Waterman
944f56a766
remove duplicate definitions
2013-02-28 14:55:19 -08:00
Andrew Waterman
1945fa898b
make external clock divider programmable
2013-01-24 23:40:47 -08:00
Andrew Waterman
62a3ea4113
fix some LLC bugs
2012-07-11 17:56:39 -07:00
Andrew Waterman
0aa33bf909
fix some LLC bugs
2012-07-11 17:56:39 -07:00
Andrew Waterman
1ebfeeca8a
add L2$
...
It still has performance bugs but no correctness bugs AFAIK.
2012-07-10 05:23:29 -07:00
Andrew Waterman
66cf690261
add L2$
...
It still has performance bugs but no correctness bugs AFAIK.
2012-07-10 05:23:29 -07:00
Andrew Waterman