Henry Cook
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a1f04386f7
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Headerless TileLinkIO and arbiters
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2015-03-09 16:34:59 -07:00 |
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Henry Cook
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002f1a1b39
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pin outer finish header
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2015-03-09 12:40:37 -07:00 |
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Henry Cook
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df79e7ff8d
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secondary miss bug
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2015-03-05 15:51:18 -08:00 |
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Henry Cook
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8e41fcf6fc
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reduce MemIFTag size, enable non pow2 HellaFLowQueue size
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2015-03-05 15:51:02 -08:00 |
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Henry Cook
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1bed6ea498
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New metadata-based coherence API
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2015-02-28 17:32:03 -08:00 |
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Henry Cook
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0a8722e881
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bugfix for indexing DataArray of of small L2
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2015-02-17 00:37:40 -08:00 |
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Henry Cook
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0c66e70f14
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cleanup of conflicts; allocation bugfix
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2015-02-06 13:20:44 -08:00 |
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Henry Cook
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7b86ea17cf
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rename L2HellaCache to L2HellaCacheBank
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2015-02-03 19:38:01 -08:00 |
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Stephen Twigg
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3b3250339a
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Explicitely convert results of Bits Muxes to UInt
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
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2015-02-03 18:15:01 -08:00 |
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Henry Cook
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57340be72b
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doc update
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2015-02-02 01:11:13 -08:00 |
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Henry Cook
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6141b3efc5
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uncached -> builtin_type
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2015-02-02 01:02:06 -08:00 |
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Henry Cook
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e6491d351f
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Offset AMOs within beat and return old value
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2015-02-02 00:22:21 -08:00 |
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Henry Cook
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3aa030f960
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Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor.
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2015-02-01 20:37:16 -08:00 |
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Henry Cook
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7b4e9dd137
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Block L2 transactions on the same set from proceeding in parallel
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2015-02-01 20:29:23 -08:00 |
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Henry Cook
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973eb43128
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state machine bug on uncached write hits
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2015-02-01 20:29:23 -08:00 |
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Henry Cook
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f58f8bf385
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Make L2 data array use a single Mem
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2015-01-25 15:37:04 -08:00 |
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Henry Cook
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9ef00d187f
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%s/master/manager/g + better comments
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2014-12-29 22:55:58 -08:00 |
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Henry Cook
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c76b4bc21d
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TileLink doc
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2014-12-29 22:55:18 -08:00 |
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Henry Cook
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e62c71203e
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disconnect unused outer network headers
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2014-12-22 18:50:37 -08:00 |
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Henry Cook
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2ef4357ca8
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acquire allocation bugfix
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2014-12-19 17:39:23 -08:00 |
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Henry Cook
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f234fe65ce
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Initial verison of L2WritebackUnit, passes MiT2 bmark tests
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2014-12-19 03:03:53 -08:00 |
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Henry Cook
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d121af7f94
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Simplify release handling
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2014-12-18 17:12:29 -08:00 |
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Henry Cook
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bfcfc3fe18
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refactor cache params
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2014-12-17 14:28:14 -08:00 |
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Henry Cook
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ab39cbb15d
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cleanup DirectoryRepresentation and coherence params
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2014-12-15 19:24:42 -08:00 |
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Andrew Waterman
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d04da83f96
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Make data RAMs 1RW instead of 1R1W
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2014-12-15 17:36:17 -08:00 |
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Henry Cook
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6a8b66231c
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Add uncached->cached tilelink converter
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2014-12-12 17:06:03 -08:00 |
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Henry Cook
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424df2368f
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1R/W L2 data array?
Add TLDataBeats to new LLC; all bmarks pass
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2014-12-12 17:05:21 -08:00 |
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Henry Cook
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3026c46a9c
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Finish adding TLDataBeats to uncore & hub
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2014-12-12 17:04:52 -08:00 |
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Henry Cook
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2f733a60db
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Begin adding TLDataBeats to uncore
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2014-12-12 17:04:31 -08:00 |
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Henry Cook
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404773eb9f
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fix wb bug
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2014-12-03 14:22:39 -08:00 |
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Henry Cook
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05b5188ad9
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meta and data bundle refactor
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2014-11-19 15:55:25 -08:00 |
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Henry Cook
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a519a43f23
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Merge branch 'master' into new-llc
Conflicts:
src/main/scala/coherence.scala
src/main/scala/memserdes.scala
src/main/scala/tilelink.scala
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2014-11-12 16:25:25 -08:00 |
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Henry Cook
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cb7e712599
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Added uncached write data queue to coherence hub
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2014-11-12 12:55:07 -08:00 |
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Henry Cook
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82155f333e
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Major tilelink revision for uncached message types
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2014-11-11 17:36:55 -08:00 |
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Henry Cook
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35553cc0b7
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NullDirectory sharers.count fix
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2014-11-11 16:05:25 -08:00 |
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Henry Cook
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10309849b7
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Remove master_xact_id from Probe and Release
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2014-11-06 12:07:33 -08:00 |
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Henry Cook
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27c72e5eed
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nearly all isa tests pass
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2014-10-23 21:50:03 -07:00 |
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Henry Cook
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a891ba1d46
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more correct handling of internal state
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2014-10-21 17:40:30 -07:00 |
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Henry Cook
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044b19dbc1
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Compiles and elaborates, does not pass asm tests
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2014-10-15 11:46:35 -07:00 |
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Henry Cook
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86bdbd6535
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new tshrs, compiles but does not elaborate
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2014-10-07 22:33:10 -07:00 |
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Henry Cook
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394eb38a96
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temp; converted voluntary wb tracker
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2014-10-03 01:06:49 -07:00 |
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Henry Cook
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dc1a61264d
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initial version, acts like old hub
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2014-10-03 01:06:49 -07:00 |
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Henry Cook
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d735f64110
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Parameter API update
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2014-10-02 16:47:35 -07:00 |
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Henry Cook
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7571695320
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Removed broken or unfinished modules, new MemPipeIO converter
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2014-09-24 15:11:24 -07:00 |
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Henry Cook
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82fe22f958
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support for multiple tilelink paramerterizations in same design
Conflicts:
src/main/scala/cache.scala
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2014-09-24 11:30:40 -07:00 |
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Henry Cook
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53b8d7b031
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use new coherence methods in l2, ready to query dir logic
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2014-09-20 18:01:14 -07:00 |
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Henry Cook
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149d51d644
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more coherence API cleanup
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2014-09-20 16:57:13 -07:00 |
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Henry Cook
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faed47d131
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use thunk for dir info
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2014-09-20 16:54:28 -07:00 |
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Henry Cook
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f7b1e23ead
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functional style on MuxBundle
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2014-09-20 16:54:28 -07:00 |
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Yunsup Lee
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f249da1803
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update README
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2014-09-17 11:25:14 -07:00 |
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