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a1b7774f5d
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Simplify handling of CAUSE register
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2014-01-24 16:37:39 -08:00 |
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6ba2c1abe5
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Use auto-generated CAUSE constants
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2014-01-21 15:01:54 -08:00 |
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57f4d89c90
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Generate D$ replay_next signals correctly
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2014-01-16 00:16:09 -08:00 |
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31060ea8ae
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Fix fubar long-latency writeback control logic
Load miss writebacks happening at the same time as multiplication
wasn't working. Hopefully this does it.
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2014-01-14 04:02:43 -08:00 |
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e8486817e6
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Clean up formatting (i.e. remove tabs, semicolons)
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2014-01-13 21:43:56 -08:00 |
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07a91bb99a
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Miscellaneous cleanup
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2013-12-09 19:53:14 -08:00 |
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da3135ac9b
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Begin integer unit clean-up
...to make it easier to generate the superscalar version of the core.
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2013-12-09 15:06:13 -08:00 |
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16d5250924
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Correct FP trap behavior on FCSR
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2013-12-05 04:18:04 -08:00 |
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924261e2b2
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Update to new privileged ISA... phew
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2013-11-25 04:35:15 -08:00 |
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65b8340cea
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Mitigate D$ hit -> branch -> NPC critical path
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2013-11-24 14:21:03 -08:00 |
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3532ae0b79
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From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator).
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2013-09-24 10:54:09 -07:00 |
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1d2f4f8437
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New ISA encoding, AUIPC semantics
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2013-09-21 06:32:40 -07:00 |
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f12bbc1e43
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working RoCC AccumulatorExample
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2013-09-14 22:34:53 -07:00 |
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a0cb711451
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Start adding RoCC
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2013-09-14 15:31:50 -07:00 |
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d053bdc89f
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Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
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2013-09-12 22:34:38 -07:00 |
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59f5358435
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Implement AQ/RL; move fence logic out of cache
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2013-09-12 16:07:30 -07:00 |
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243c4ae342
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sync up rocket with new isa
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2013-09-12 03:44:38 -07:00 |
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d1b5076fee
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Don't update BTB when garbage was fetched
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2013-08-24 14:44:11 -07:00 |
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52e31f3298
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Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
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2013-08-24 14:44:04 -07:00 |
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
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b570435847
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Reg standardization
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2013-08-13 17:50:02 -07:00 |
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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c837c1d800
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fix bug in previous JALR commit
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
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2013-05-21 18:28:44 -07:00 |
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28f914c3f2
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don't JALR to speculatively-bypassed addresses
Technically not necessary, but probably improves performance.
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2013-05-21 16:56:58 -07:00 |
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3a1b5f01b2
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don't take interrupts while they're disabled!
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
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2013-05-19 23:27:47 -07:00 |
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50ccc20bf3
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replace RDNPC with AUIPC
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2013-04-22 04:20:15 -07:00 |
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8cbdeb2abf
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add LR/SC support
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2013-04-04 17:07:09 -07:00 |
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fc46daecf6
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don't flush pipeline on writes to side-effect-free PCRs
notably, K0, K1, and EPC
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2013-04-04 17:07:09 -07:00 |
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d4a3351cfc
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expose pending interrupts in status register
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2013-04-04 17:07:08 -07:00 |
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575bd3445a
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re-generalize scoreboard
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2013-01-24 18:00:39 -08:00 |
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63060bc0a8
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minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
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2013-01-23 19:27:53 -08:00 |
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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05f19b21d0
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merge multiplier and divider
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2012-12-12 02:22:47 -08:00 |
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9c857b83f0
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refactor PCR file
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2012-11-27 01:28:06 -08:00 |
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352bb464b5
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clock gate X/M and M/W store data registers
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2012-11-26 20:33:41 -08:00 |
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de2f28193a
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get rid of more global constants
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2012-11-25 04:24:25 -08:00 |
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c036cdc1ea
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add option for 2-cycle load-use delay
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2012-11-24 22:01:08 -08:00 |
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29bc361d6c
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remove global constants; disentangle hwacha a bit
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2012-11-17 17:24:08 -08:00 |
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5a7777fe4d
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clock gate integer datapath more aggressively
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2012-11-17 06:48:44 -08:00 |
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8dce89703a
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new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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ff8c736d94
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move icache invalidate out of request bundle
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2012-11-16 01:55:45 -08:00 |
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be1980dd2d
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refactored vector queue interface
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2012-11-07 01:15:33 -08:00 |
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4d1ca8ba3a
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remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
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2012-11-06 08:13:44 -08:00 |
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e76892f758
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remove more global constants
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2012-11-06 02:55:45 -08:00 |
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c5b93798fb
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factor out more global constants
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2012-11-05 23:52:32 -08:00 |
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5b20ed71be
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move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
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2012-11-05 01:30:57 -08:00 |
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7380c9fe60
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aggressively clock gate int and fp datapaths
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2012-11-04 16:40:14 -08:00 |
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88ac5af181
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Merged consts-as-traits
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2012-10-16 16:32:35 -07:00 |
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