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Commit Graph

651 Commits

Author SHA1 Message Date
Howard Mao
9b9c662952 fix w_last wire 2016-03-29 20:16:07 -07:00
Howard Mao
2b61f28356 don't test DMA controller for now 2016-03-29 20:16:07 -07:00
Howard Mao
e1a03cc9ac fix issue with partial writemasks 2016-03-29 20:16:07 -07:00
Andrew Waterman
6c48dc3471 Use more sensible knob values for SmallConfig 2016-03-25 14:18:24 -07:00
Andrew Waterman
cce89f5fbc Bump rocket 2016-03-25 14:18:15 -07:00
Andrew Waterman
d1639416cb Merge pull request #77 from ucb-bar/chisel3
Preliminary Chisel 3 Support
2016-03-24 12:56:36 -07:00
Palmer Dabbelt
39cf945efb Use Chisel 3 to build verilog on Travis
Chisel 3 can't build the C++ emulator, so we currently can't have direct
support for testing RocketChip.  We can at least test to see if the
Verilog builds when run through Chisel 3, which this patch does.
2016-03-24 12:00:13 -07:00
Palmer Dabbelt
cddfdf0929 Add CHISEL_VERSION make argument
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3.  Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
Palmer Dabbelt
d697559754 Correct the polarity of the non-backup-memory HTIF
This fails in FIRRTL because <> has polarity now.
2016-03-24 12:00:13 -07:00
Palmer Dabbelt
7d5eac189b Bump the uncore for some Chisel3 fixes 2016-03-24 12:00:13 -07:00
Palmer Dabbelt
4744deec28 Fix the SCR file for Chisel 3 2016-03-24 12:00:13 -07:00
Palmer Dabbelt
476db6ef39 Move to a newer Scala version
Chisel3 needs a newer version of Scala to run correctly.
2016-03-24 12:00:13 -07:00
Matthew Naylor
6da45e7f26 Trace generator: updates and additions to the scripts directory.
(1) Introduce tracegen.py, a script that invokes the emulator (built
    with TraceGenConfig), sending a SIGTERM once all cores are finished.

(2) Update toaxe.py to gather some statistics about the trace.

(3) Introduce tracestats.py, which displays the stats in a useful way.

(4) Introduce tracegen+check.py, a top-level script that generates
    traces, checks them, and emits stats.  If this commit is pulled, it
    should be done after pulling my latest groundtest commit.
2016-03-21 15:28:15 -07:00
Palmer Dabbelt
c989ec5813 Fix the SCR file for Chisel 3 2016-03-21 11:55:40 -07:00
Colin Schmidt
b5992186df include top-level makefrag in regressions
fixes issue with rocketchip_addons inclusion
2016-03-16 15:52:28 -07:00
Howard Mao
e90a9dfb2b make taking max of multiple integers in config a bit easier 2016-03-16 14:35:08 -07:00
Eric Love
4fc2a14a63 Fix MIF bug that cuts off upper xact id bits 2016-03-16 13:50:30 -07:00
Andrew Waterman
9dc0cbdfa4 WIP on privileged spec v1.9 2016-03-14 18:03:33 -07:00
Andrew Waterman
648437e7cb Merge pull request #70 from ucb-bar/add-rv32-support
Add RV32 test/configuration options
2016-03-14 17:06:39 -07:00
Andrew Waterman
f2ded2721d Merge branch 'master' into add-rv32-support 2016-03-10 19:33:04 -08:00
Andrew Waterman
25091003af Add RV32 test/configuration options
These won't actually work until further commits.  Rocket RV32 support
is complete, but on the priv-1.9 branch.
2016-03-10 17:40:21 -08:00
Andrew Waterman
67ad36d74a Merge pull request #69 from ucb-bar/fix-tabs
tabs are evil
2016-03-10 16:17:46 -08:00
Andrew Waterman
7a75a03123 tabs are evil 2016-03-10 14:18:56 -08:00
Howard Mao
3c9e63f5a5 don't make HTIF clock divider tied to backup memory 2016-03-09 14:58:20 -08:00
Howard Mao
5e145515e1 fix some Chisel assertions 2016-03-02 14:50:49 -08:00
Colin Schmidt
9c7e5bc6c0 bump hardfloat, tools(tests & spike) for fcvt fix 2016-03-01 19:53:26 -08:00
Albert Magyar
a80b0e959d Add support for per-way cache metadata
Adds a new cache parameter (SplitMetadata) and an associated knob.

Closes #62
2016-03-01 13:03:24 -08:00
Colin Schmidt
a9380a3dc1 bump hardfloat,uncore,chisel,tools(tests) for sqrt fix 2016-02-29 16:59:55 -08:00
Howard Mao
760893e448 add makefile for float_fix and comlog tools 2016-02-29 11:24:53 -08:00
Howard Mao
be8a411f9c get rid of axe submodule and move toaxe.py script to scripts 2016-02-29 10:59:19 -08:00
John Wright
ba96ad2b38 Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip 2016-02-27 16:24:45 -08:00
Palmer Dabbelt
7fa38b5624 Merge pull request #68 from ucb-bar/test-and-fix-backup-mem
Fix the backup memory port
2016-02-27 12:19:55 -08:00
Palmer Dabbelt
a0f3189c74 Change MIF_DATA_BITS back to 64
It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM.  Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.

Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
2016-02-27 11:43:44 -08:00
Palmer Dabbelt
9ea8c4e781 Add an 8-channel backup memory port config
Now that the backup memory port works I want to test it.
2016-02-27 10:56:13 -08:00
Palmer Dabbelt
7319f430d0 Fix the backup memory port on multiple-channel configs
The backup memory port doesn't work on multi-channel configurations, it
just screws up the Nasti tag bits.  This patch always instantiates a
single-channel backup memory port, which relies on the memory channel
selector to only enable a single memory channel when the backup memory
port is enabled.  There are some assertions to make sure this happens,
as otherwise memory gets silently corrupted.

While this is a bit of a hack, the backup memory port will be going away
soon so I don't want to spend a whole lot of time fixing it.  The
generated hardware is actually very similar: we used to elaborate a
Nasti arbiter inside the backup memory support, now there's one outside
of it instead.
2016-02-27 10:47:52 -08:00
Palmer Dabbelt
7c0c48fac4 Resurrect the backup memory port
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
2016-02-27 10:46:56 -08:00
Colin Schmidt
68a49c7700 fetch rocketchip_addons during regression submodule step 2016-02-26 11:05:41 -08:00
Palmer Dabbelt
8c73d10fe1 Support SCR address generation with __OFFSET at the end 2016-02-25 21:57:37 -08:00
Andrew Waterman
640204b221 Merge pull request #66 from ucb-bar/rocc-ptw-refactoring
RoCC PTW refactoring
2016-02-25 18:01:01 -08:00
Yunsup Lee
a2381d2faf RoCC PTW refactoring 2016-02-25 17:26:42 -08:00
Colin Schmidt
ef4915bd2c make the asm suites ordered by their insertion order 2016-02-24 19:49:35 -08:00
Colin Schmidt
ad81d95751 add run-asm-{p,pt,v}-tests targets for convenience 2016-02-24 19:49:35 -08:00
John Wright
b04cd545b6 pass base SCR address to SCRFile for address calculation 2016-02-24 15:32:46 -08:00
Howard Mao
8a877fa620 Add Matthew Naylor's trace generator and AXE scripts 2016-02-24 14:39:11 -08:00
Howard Mao
8c02cb09ca some additions to Travis and fixes for Testing 2016-02-23 23:37:29 -08:00
Palmer Dabbelt
90a73c621d Merge pull request #58 from ucb-bar/more-travis-fixing
More travis fixing
2016-02-23 21:26:16 -08:00
Palmer Dabbelt
58d6af207f Cache all the Scala build directories
I hope this will result in Travis building our stuff a lot faster, since this
currently takes about half the time.
2016-02-23 16:47:48 -08:00
Palmer Dabbelt
c263c636b3 Actually reference all the tests from RISCV 2016-02-23 16:05:27 -08:00
Palmer Dabbelt
ad62afd9ca Add zscale to regression submodule list 2016-02-23 12:58:08 -08:00
Palmer Dabbelt
700d756de0 Merge pull request #55 from ucb-bar/travis-regression
travis-ci.org improvements
2016-02-23 12:19:59 -08:00