Henry Cook
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1b3307df32
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Removed has_data fields from all coherence messages, increased message type names to compensate
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2012-03-02 23:51:53 -08:00 |
|
Andrew Waterman
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012da6002e
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replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
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2012-02-29 03:10:47 -08:00 |
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Andrew Waterman
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c99f6bbeb7
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separate memory request command and data
also, merge some VLSI/C++ test harness functionality
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2012-02-28 19:06:23 -08:00 |
|
Andrew Waterman
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2b1c07c723
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replace ioDCache with ioMem
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2012-02-27 18:36:09 -08:00 |
|
Andrew Waterman
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ad713a5d83
|
fix icache ram depth; new chisel
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2012-02-26 17:51:46 -08:00 |
|
Huy Vo
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5b0f7ccf68
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updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
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2012-02-26 17:24:08 -08:00 |
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Yunsup Lee
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94ba32bbd3
|
change package name and sbt project name to rocket
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2012-02-25 17:09:26 -08:00 |
|
Andrew Waterman
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6135615104
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unify cache backend interfaces; generify arbiter
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2012-02-20 00:51:48 -08:00 |
|
Andrew Waterman
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725190d0ee
|
update to new chisel
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2012-02-11 17:20:33 -08:00 |
|
Christopher Celio
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1be9d15944
|
Fixed bug regarding case sensitivity regarding ioICache,ioDCache
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2012-02-07 14:07:42 -08:00 |
|
Henry Cook
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c5a4eaa0a1
|
Associative cache, boots kernel
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2012-02-01 13:26:04 -08:00 |
|
Andrew Waterman
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97c379f1d7
|
made I$ associative
|
2012-01-24 16:51:30 -08:00 |
|
Andrew Waterman
|
7f26fe2c44
|
make icache size parameterizable
|
2012-01-24 15:13:49 -08:00 |
|
Andrew Waterman
|
a5a020f97b
|
update chisel and remove SRAM_READ_LATENCY
|
2012-01-23 20:59:38 -08:00 |
|
Henry Cook
|
1d76255dc1
|
new chisel version jar and find and replace INPUT and OUTPUT
|
2012-01-18 14:39:57 -08:00 |
|
Andrew Waterman
|
addfe55735
|
add FPGA memory generator script
|
2012-01-13 18:19:08 -08:00 |
|
Andrew Waterman
|
4807d7222b
|
use replay to handle I$ misses
this eliminates a long path in the fetch stage
|
2012-01-11 19:20:20 -08:00 |
|
Andrew Waterman
|
1a7bfd4350
|
remove icache req_rdy signal
|
2012-01-11 18:27:11 -08:00 |
|
Andrew Waterman
|
a8d0cd95e6
|
hellacache now works
|
2011-12-17 03:26:11 -08:00 |
|
Andrew Waterman
|
56c4f44c2a
|
hellacache returns!
but AMOs are unimplemented.
|
2011-12-12 06:49:39 -08:00 |
|
Andrew Waterman
|
218f63e66e
|
code cleanup/parameterization
|
2011-12-09 00:42:43 -08:00 |
|
Rimas Avizienis
|
fa784d1d7d
|
made setReadLatency argument a parameter defined in consts.scala
|
2011-12-05 00:33:17 -08:00 |
|
Rimas Avizienis
|
ff95cacb55
|
icache/dcache tag+data arrays now implemented using Mem4()
however there seems to be a bug - readLatency needs to be set to 0
for C model to work, and 1 for Verilog model.
|
2011-12-04 01:18:38 -08:00 |
|
Rimas Avizienis
|
e894b79870
|
caches now use Mem4() memories for tag+data arrays
|
2011-12-03 19:41:15 -08:00 |
|
Rimas Avizienis
|
c580180b66
|
tweaks to cache/SRAM interface for TSMC65 SRAMs
|
2011-12-02 02:01:08 -08:00 |
|
Rimas Avizienis
|
cf1965493b
|
renamed SRAM modules to match TSMC65 MC generated SRAMs
|
2011-12-01 13:14:33 -08:00 |
|
Rimas Avizienis
|
b791010bb1
|
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
|
2011-11-14 04:13:13 -08:00 |
|
Rimas Avizienis
|
35af912bd2
|
cache optimizations, cleanup, and testharness improvement
|
2011-11-12 22:13:29 -08:00 |
|
Rimas Avizienis
|
83d90c4dab
|
more itlb/dtlb/ptw fixes
|
2011-11-12 15:00:45 -08:00 |
|
Rimas Avizienis
|
73416f224b
|
more tlb/ptw debugging
|
2011-11-12 00:25:06 -08:00 |
|
Rimas Avizienis
|
36aa4bcc9d
|
moved exception handling from ex stage in dpath to mem stage in ctrl
|
2011-11-10 02:26:26 -08:00 |
|
Rimas Avizienis
|
c29d2821b4
|
cleanup, fixes, initial commit for dtlb.scala
|
2011-11-09 21:54:11 -08:00 |
|
Rimas Avizienis
|
e96430d862
|
integrating ITLB & PTW
|
2011-11-09 14:52:17 -08:00 |
|
Rimas Avizienis
|
9d63087eb2
|
changed caches to use separate sram modules for tag and data arrays
|
2011-11-07 00:58:25 -08:00 |
|
Rimas Avizienis
|
4d64099103
|
cleanup
|
2011-11-04 20:52:21 -07:00 |
|
Rimas Avizienis
|
c06e2d16e4
|
initial commit of rocket chisel project, riscv assembly tests and benchmarks
|
2011-10-25 23:02:47 -07:00 |
|