Henry Cook
|
302cd3e638
|
Added BuildZscale param for use in Top and makefrag generation
|
2015-07-13 15:46:42 -07:00 |
|
Henry Cook
|
407d8e473e
|
first cut at parameter-based testing
|
2015-07-13 14:54:26 -07:00 |
|
Henry Cook
|
4e4015089d
|
rename Configs source
|
2015-07-09 15:04:11 -07:00 |
|
Yunsup Lee
|
09e29e8fe0
|
add zscale
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
|
2015-07-07 20:38:47 -07:00 |
|
Yunsup Lee
|
e6a13cdeba
|
New machine-mode timer facility
Mirroring Andrew's commit to reference-chip
|
2015-07-07 17:26:07 -07:00 |
|
Henry Cook
|
4fbb0f80ff
|
Added some multicore/multibanks named ChiselConfigs
|
2015-07-06 18:21:06 -07:00 |
|
Henry Cook
|
d3ccec1044
|
Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
|
2015-07-02 14:43:30 -07:00 |
|
Yunsup Lee
|
702ddabe26
|
add ExampleSmallConfig for README
|
2014-10-07 02:07:59 -07:00 |
|
Yunsup Lee
|
e25d420155
|
Improve ChiselConfig composability; bump chisel
|
2014-10-06 13:43:40 -07:00 |
|
Yunsup Lee
|
73eac94a65
|
Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
|
2014-10-06 13:40:35 -07:00 |
|
Henry Cook
|
122733b3a9
|
file name consistency
|
2014-10-06 13:37:38 -07:00 |
|
Henry Cook
|
0b5f23a209
|
Streamlined uncore for release
|
2014-10-06 13:37:15 -07:00 |
|
Adam Izraelevitz
|
15fb4730ec
|
Add BuildTile parameter for Tile
Conflicts:
rocket
|
2014-09-25 06:50:45 -07:00 |
|
Henry Cook
|
7398b00d93
|
dir supplied by function
|
2014-09-25 06:50:41 -07:00 |
|
Henry Cook
|
5a840c5520
|
support for multiple tilelink paramerterizations in same design
|
2014-09-25 06:50:30 -07:00 |
|
Donggyu Kim
|
eb384f6461
|
new RocketChipBackend implementation
|
2014-09-25 06:47:12 -07:00 |
|
Scott Beamer
|
f2ca887de3
|
better fpga configs
|
2014-09-25 06:47:03 -07:00 |
|
Donggyu Kim
|
4fe48f5a0a
|
bump chisel
|
2014-09-25 06:46:58 -07:00 |
|
Donggyu Kim
|
60d90f5230
|
recover collectNodesIntoComp in Backends.scala
|
2014-09-25 06:46:50 -07:00 |
|
Donggyu Kim
|
a53091b40f
|
remove collectNodesIntoComp from Backends.scala
|
2014-09-25 06:46:27 -07:00 |
|
Scott Beamer
|
f4e6cd75ab
|
turn off fpu for default fpga config.
a larger fpga can use defaultconfig
|
2014-09-25 06:46:16 -07:00 |
|
Yunsup Lee
|
09de2e2794
|
compute number of outstanding misses for DRAMSideLLCNull
|
2014-09-12 18:09:38 -07:00 |
|
Yunsup Lee
|
1cfd9f5a0e
|
add LICENSE
|
2014-09-12 10:15:04 -07:00 |
|
Yunsup Lee
|
c98afa1fea
|
turn off DRAMSideLLC
|
2014-09-11 22:10:25 -07:00 |
|
Yunsup Lee
|
b5a64487eb
|
turn off DRAMSideLLC
|
2014-09-11 22:07:44 -07:00 |
|
Yunsup Lee
|
02c08a156f
|
generate consts.vh from chisel source
|
2014-09-10 17:14:55 -07:00 |
|
Yunsup Lee
|
6b6bdd2b83
|
decommission Slave top-level module for fpga build
|
2014-09-08 00:23:15 -07:00 |
|
Yunsup Lee
|
ddfd3ce968
|
further generalize fpga/vlsi builds
|
2014-09-08 00:21:57 -07:00 |
|
Henry Cook
|
ae05125f29
|
Adjustements to top-level parameters and knobs for hwacha
|
2014-09-07 17:57:33 -07:00 |
|
Henry Cook
|
4126678c9d
|
Merge branch 'dse'
Conflicts:
rocket
uncore
|
2014-09-06 06:59:14 -07:00 |
|
Henry Cook
|
82467313dd
|
merge in rocketchip changes from master
|
2014-09-02 13:51:57 -07:00 |
|
Yunsup Lee
|
7734285507
|
forgot to comment out hwacha
|
2014-09-01 09:01:36 -07:00 |
|
Yunsup Lee
|
c03c09ec31
|
update for rocket-chip release
|
2014-08-31 20:26:55 -07:00 |
|
Henry Cook
|
78ab83d224
|
refactor fpga top/config
|
2014-08-28 13:07:54 -07:00 |
|
Henry Cook
|
bf356b9cb4
|
Refactor to combine fpga and vlsi tops, part 1
|
2014-08-24 19:30:53 -07:00 |
|
Henry Cook
|
a41d55b643
|
Final parameter refactor.
|
2014-08-23 01:26:03 -07:00 |
|
Scott Beamer
|
63b62394d9
|
added l2 to fpga
with new chisel & uncore, it goes into brams
|
2014-08-20 15:41:07 -07:00 |
|
Henry Cook
|
1563c1bb36
|
Fixed cache params. Asm and bmark tests pass.
|
2014-08-12 15:00:54 -07:00 |
|
Henry Cook
|
7f07771600
|
Cache utility traits. Completely compiles, asm tests hang.
|
2014-08-11 18:37:10 -07:00 |
|
Henry Cook
|
1983260e6f
|
a few more fixes. some param lookups fail (here() in Alter blocks)
|
2014-08-10 23:08:21 -07:00 |
|
Henry Cook
|
63bd0b9d2a
|
Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
|
2014-08-08 12:27:47 -07:00 |
|
Adam Izraelevitz
|
08d81d0892
|
First cut at using new chisel parameters for toplevel parameters and fpu
|
2014-08-01 18:09:37 -07:00 |
|
Henry Cook
|
434da22283
|
Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel)
|
2014-05-28 17:16:49 -07:00 |
|
Henry Cook
|
b0ccb88982
|
make outer cache type choice a top-level const
|
2014-05-28 14:46:07 -07:00 |
|
Henry Cook
|
ce056b4b89
|
client/master -> inner/outer
|
2014-04-29 16:50:30 -07:00 |
|
Henry Cook
|
224e286dd3
|
New uncore config objects. Backends get their own file. Simplify fpga uncore.
|
2014-04-26 19:46:11 -07:00 |
|
Henry Cook
|
3d4273954a
|
TileLinkIO.GrantAck -> TileLinkIO.Finish
|
2014-04-26 15:19:25 -07:00 |
|
Henry Cook
|
fbf6e44376
|
fix connection error in fpga uncore
|
2014-04-24 11:58:59 -07:00 |
|
Henry Cook
|
cfd6748318
|
patches to make FAME1/dram IOs compile with up-to-date chisel (bumped)
|
2014-04-21 17:26:33 -07:00 |
|
Henry Cook
|
2cb4dbae39
|
Refactored uncore constants and tilelink data
|
2014-04-10 13:19:50 -07:00 |
|