riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao
66b9c5ad05 fix up cloneType calls in clock crossers 2016-07-13 14:31:19 -07:00
Wesley W. Terpstra
eeae74e3fc nasti: include convenient clock crossing helpers 2016-07-13 14:20:25 -07:00
Wesley W. Terpstra
c33c0944be crossing: first clock crossing, the handshaker 2016-07-13 14:20:25 -07:00
Howard Mao
18ea58c85f remove unnecessary CAMs from converters 2016-07-13 12:42:50 -07:00
Howard Mao
b122a54c32 don't allow more outer IDs than inner IDs 2016-07-13 12:42:28 -07:00
Howard Mao
37fd11870c fix up ReorderQueue CAM 2016-07-13 12:11:43 -07:00
Howard Mao
de1e25f3d1 reduce usage of CAMs in converters 2016-07-13 11:20:50 -07:00
Howard Mao
c0dc09b3a1 don't use CAM in ReorderQueue if not necessary 2016-07-13 11:08:15 -07:00
Howard Mao
f3775df04d fix the condition under which comparator error signal is set 2016-07-12 18:37:13 -07:00
Howard Mao
4c79215fde add a script for checking comparator trace 2016-07-12 14:42:04 -07:00
Howard Mao
88dc0b983a make sure Comparator logs correctly when prefetching off 2016-07-12 14:36:46 -07:00
Howard Mao
676a536706 fix bugs from adding ComparatorSource backpressure 2016-07-12 13:50:34 -07:00
Howard Mao
d435bb4185 reduce hardware usage of Comparator to allow it to synthesize 2016-07-12 10:54:18 -07:00
Palmer Dabbelt
2f70136f90 Fix the Nasti to Smi Converter for single-word Nasti busses 
There's a register that tracks what word within a Nasti transaction a
Smi response cooresponds to, since Smi itself doesn't have any
multi-word stuff.  This breaks the single-word Nasti to Smi converter
due to what's essentially a 0-width wire bug: it ends up doing something
like

  word_offset_into_nasti := nasti_address(3, 3)

when "word_offset_into_nasti" should really be a 0-bit register, but due
to some log2Up block size calculation logic it's actually a 1-bit
register.  Thus, this expression ends up grabbing a bit of the address,
which causes odd addresses to get buffered incorrectly.

My fix is to just special-case the "Nasti bus width is the same as Smi
bus width" case.
 2016-07-12 09:31:21 -07:00
Howard Mao
90bcd3dbdc make sure DirectGroundTest testers given correct TL settings 2016-07-11 18:11:01 -07:00
Howard Mao
8f0fa11ce4 optionally export detailed status information in DirectGroundTest 2016-07-11 18:11:00 -07:00
Howard Mao
b64998ec05 make sure dramsim reads and writes occur in the order they are received 2016-07-11 18:11:00 -07:00
Howard Mao
cb2a18b533 allow direct instatiation of arbitrary non-caching groundtests 2016-07-11 18:11:00 -07:00
Howard Mao
f03ffb32a0 add top that directly tests the TL -> AXI converters 2016-07-11 18:11:00 -07:00
Howard Mao
b47f8fbc41 don't use splat and bug out if too many address map entries 2016-07-11 18:10:42 -07:00
Howard Mao
18967642de export more detailed status data from GroundTest 2016-07-11 16:41:55 -07:00
Wesley W. Terpstra
46fc9744e2 rocket: add an AXI master port into the chip 2016-07-11 12:16:44 -07:00
Wesley W. Terpstra
8ac7fa5544 ext: support multiple external AHB/AXI ports 2016-07-11 12:16:39 -07:00
Howard Mao
e194677087 fix comparator PutBlock data generation and debug output 2016-07-11 12:15:37 -07:00
mwachs5
36720d915a Update README.md (#161) 
Correct typo in heading
 2016-07-11 00:34:13 -07:00
Andrew Waterman
9751ea0f35 Fix Verilator VCD (#157) 2016-07-09 02:37:39 -07:00
Andrew Waterman
1699622730 Don't speculatively refill I$ in uncacheable regions 2016-07-09 01:10:58 -07:00
Howard Mao
5a3d6a1583 NastiTest should cycle through write ids 2016-07-08 17:55:02 -07:00
Howard Mao
9ec55ebb91 don't add io:ext region to address map if no external MMIO 2016-07-08 15:29:35 -07:00
Howard Mao
35547aa428 allow NastiConverterTest and Memtest to run simultaneously 2016-07-08 13:40:52 -07:00
Howard Mao
d80c2f480f make NastiConverterTest act as generator and share blocks 2016-07-08 13:39:46 -07:00
Howard Mao
358668699f refactoring groundtest configuration 2016-07-08 11:40:16 -07:00
Howard Mao
850fa092a4 refactor how groundtests are configured 2016-07-08 11:40:01 -07:00
Howard Mao
eeac405ef8 get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache 2016-07-08 09:33:07 -07:00
Howard Mao
8aa73915a1 put locking arbiter back into converter 2016-07-08 09:31:33 -07:00
Howard Mao
a50ba39ea7 Revert "add buffering and locking to TL -> Nasti converter" 
This reverts commit 2109a48e18719383942d535ff4c1d0a859dcc424.

Conflicts:
	src/main/scala/converters/Nasti.scala
 2016-07-08 09:31:33 -07:00
Andrew Waterman
32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
Andrew Waterman
70b677ecda Vec considered harmful; use isOneOf instead (#64) 
Vec is heavyweight and really should only be used for I/O and
dynamic indexing.  A recurring pattern in uncore is

    Vec(const1, const2, const3) contains x

which is nice but has a deleterious effect on simulation copilation
and execution time.  This patch proposes an alternative:

    x isOneOf (const1, const2, const3)
    x isOneOf seqOfThings

I think it's also more idiomatic.

This is just a prototype; I'm not wed to the name or implementation.
 2016-07-07 19:25:57 -07:00
Howard Mao
f7b392306e make sure SimpleHellaCacheIF can work with blocking DCache 2016-07-07 18:59:23 -07:00
Howard Mao
f62c74b82a allow groundtest to use non-blocking DCache 2016-07-07 18:59:09 -07:00
Andrew Waterman
3d8939d3c3 Set misa.base = 1 for RV32 2016-07-07 15:32:21 -07:00
Andrew Waterman
2455a806af Make WFI instruction respect mie CSR setting 2016-07-07 15:31:17 -07:00
Howard Mao
67871654dd start NastiConverterTest higher up in memory 2016-07-07 14:35:04 -07:00
Howard Mao
16a6b11081 fix bug in AXI -> TL converter 2016-07-07 14:34:24 -07:00
Howard Mao
7cc64011fb simplify amo_mask generation 2016-07-07 12:14:45 -07:00
Howard Mao
1c5e7be75b make sure Nasti write channel id is set correctly 2016-07-07 12:14:02 -07:00
Howard Mao
6055482513 make sure write channel id is actually set 2016-07-07 12:12:39 -07:00
Howard Mao
8ccc50a8f0 fix IdMapper and TL -> NASTI converter 2016-07-07 10:16:44 -07:00
Howard Mao
8c13e78ab5 add buffering and locking to TL -> AXI converter 2016-07-06 16:57:09 -07:00
Howard Mao
e27cb5f885 fix voluntary release issue in L2 cache 2016-07-06 16:57:01 -07:00