riscv/rocket-chip
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Author SHA1 Message Date
Palmer Dabbelt
62257e0b04 Uncomment MemSerializedIO.cloneType() 
Not sure why this was commented, but when I build this against Chisel3 it fails
without this override.
 2016-02-04 15:28:46 -08:00
Palmer Dabbelt
be424633c1 Improve ParamaterizedBundle.cloneType()'s error messages 
Without this it's really hard to read the IllegalArgumentException that you get
if you subclass ParamaterizedBundle and don't define a matching cloneType().
 2016-02-04 15:26:42 -08:00
Howard Mao
5abfd1a4ab make sure to check for region violations in DMA frontend 2016-02-03 15:40:44 -08:00
Colin Schmidt
c944193e16 add dma configs to travis 2016-02-02 16:06:01 -08:00
Howard Mao
06c3f9b655 Rocket Chip fixes in response to lowRISC team's comments 
* DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable
 2016-02-02 13:14:52 -08:00
Howard Mao
60d9291cb5 rename external to nastiExternal to avoid name conflicts 2016-02-02 13:14:04 -08:00
Howard Mao
bfdf5a538a Separate memory interconnect from IO interconnect. 
Since we're separating memory and MMIO traffic in the L1 to L2 network,
we won't need to route between memory and MMIO at the AXI interconnect.
This means we can have separate (and simpler) AXI interconnects for
each. One consequence of this is that the starting address of the IO
interconnect can no longer be assumed to be 0 by default.
 2016-02-02 13:14:04 -08:00
Howard Mao
66e9cc8c82 make sure CSR width is parameterizable 2016-02-02 12:49:58 -08:00
Howard Mao
adaec18bec add TL manager for MMIO requests 2016-02-02 12:49:58 -08:00
Howard Mao
c1fe188c81 some fixes to RTC 2016-02-02 12:49:58 -08:00
Howard Mao
ba94010928 DMA requests should go through MMIO 2016-02-02 12:49:58 -08:00
Palmer Dabbelt
97640f099d Merge pull request #41 from ucb-bar/regressions 
Support torture regressions
 2016-02-01 18:39:28 -08:00
Palmer Dabbelt
5cea4edee2 Bump riscv-tools for torture NaN ISA change 2016-01-31 23:06:59 -08:00
Palmer Dabbelt
e18759642f Avoid running Chisel in parallel in the same directory 
It looks like Chisel fails when I try to run it in parallel.  This adds a lock
file to ensure that only a single Chisel instance is running at a time when
running the regressions.
 2016-01-31 23:06:59 -08:00
Palmer Dabbelt
00465b15c3 Allow the regression Makefile to clean all targets 2016-01-31 23:06:59 -08:00
Palmer Dabbelt
c9a2b7d109 Add torture as part of the regression 
Since the latest Spike fix my torture runs are succeeding, so I can now run it
as part of the regression flow.
 2016-01-31 23:06:59 -08:00
Palmer Dabbelt
e185fe6850 Add targets for emulator and fsim regressions 
This change allows the other simulation targets (the emulator and the FPGA
simulator) to be run just like the Verilog simulator could be before.
 2016-01-31 23:06:59 -08:00
Howard Mao
78579672d3 make mtvec configurable and writeable 2016-01-29 14:51:56 -08:00
Howard Mao
7937fbf074 fix number of IOMSHRs at 1 2016-01-29 14:51:56 -08:00
Howard Mao
305185c034 send DMA requests through MMIO and get responses through CSRs 2016-01-29 14:51:56 -08:00
Andrew Waterman
7e9d8c7256 Merge pull request #40 from ucb-bar/make-3.82 
Support make-3.82 and newer
 2016-01-28 14:28:27 -08:00
Palmer Dabbelt
1149a412cc Support make-3.82 and newer 
make changed its priorties for resolving implicit rules, which causes different
behavior when running "make run-bmark-tests".  This patch changes the hex file
rules to ensure they match between the two versions of make.

I've tried this with both make-3.81 and make-4.1, and they both work for me.
 2016-01-28 12:19:11 -08:00
Andrew Waterman
58fcc6b7c6 Get rid of useless mux 2016-01-28 11:44:59 -08:00
Howard Mao
428fa14601 fix DummyPTW response 2016-01-27 15:33:02 -08:00
Howard Mao
a59ff38b67 use MMIO for DMA requests instead of separate channel 2016-01-27 15:33:02 -08:00
Palmer Dabbelt
7209c13338 Move to a regression Makefile 
In order to have the buildbot support various types of failures it needs
to run different commands.  Rather than modifying the regression script
to have a bunch of arguments I've just gone and made a makefile for
regressions instead.

This doesn't run torture right now because that's broken, but I'll add
support soon.
 2016-01-26 22:50:49 -08:00
Andrew Waterman
a56a502ced Add missing cloneType method 
@zhemao
 2016-01-23 21:36:16 -08:00
Howard Mao
ff79a44eb0 move some utility code from uncore to junctions 2016-01-21 15:39:09 -08:00
Howard Mao
d170fcd913 DecoupledHelper is now imported from junctions 2016-01-21 15:38:43 -08:00
Howard Mao
19c526de59 move ReorderQueue and DecoupledHelper in from uncore 2016-01-21 15:37:07 -08:00
Howard Mao
0dc8cd5b11 move ReorderQueue and DecoupledHelper to junctions 2016-01-21 15:36:22 -08:00
Howard Mao
6a0352c6d0 fix up SmiMem 2016-01-20 23:25:16 -08:00
Andrew Waterman
52d6b0b1a5 Improve ALU QoR 
Rejigger muxes; share XOR gates between ADD/SUB, XOR, and BEQ.
 2016-01-20 17:42:31 -08:00
Andrew Waterman
fdd19145e9 bump chisel/hardfloat/junctions/uncore submodules 2016-01-17 01:50:04 -08:00
Andrew Waterman
2946bc928e Avoid muxing between bundles of different size 2016-01-16 19:01:24 -08:00
Howard Mao
04fd407c3e bump rocket submodule pointer 2016-01-15 15:29:23 -08:00
Andrew Waterman
335fb73120 Chisel3 compatibility fix 
No need for a Vec here.
 2016-01-15 15:17:16 -08:00
Howard Mao
77e068c153 fix Chisel3 compat issue in SimpleHellaCacheIF 2016-01-14 22:42:44 -08:00
Howard Mao
3b4b7126ed Chisel3 compile-time deprecations should be runtime errors 2016-01-14 15:12:41 -08:00
Howard Mao
33aa64212d fix more Chisel3 deprecations 2016-01-14 15:06:30 -08:00
Howard Mao
4ff1aea288 fix more Chisel3 deprecations 2016-01-14 14:55:45 -08:00
Howard Mao
120361226d fix more Chisel3 deprecations 2016-01-14 14:46:31 -08:00
Howard Mao
c8fa7c43a9 fix Chisel3 deprecation warnings 2016-01-14 13:38:00 -08:00
Howard Mao
d51c127646 fix deprecation warnings in rocket.scala 2016-01-13 22:08:06 -08:00
Andrew Waterman
fc638c6339 Chisel3 compatibility fixes 2016-01-12 16:28:05 -08:00
Andrew Waterman
ae98af7077 don't mix SInt/UInt 2016-01-12 16:27:36 -08:00
Andrew Waterman
603db5e271 Chisel3 compatibility; new NaNs; new MIPI behavior 2016-01-12 16:25:03 -08:00
Andrew Waterman
00d17abd78 Don't ignore data value when writing MIPI 2016-01-12 16:23:06 -08:00
Andrew Waterman
7bf503a275 Remove four integer/FP converters 2016-01-12 16:06:23 -08:00
Andrew Waterman
31d537c405 Add missing cloneType 2016-01-12 15:45:11 -08:00