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Author	SHA1	Message	Date
Andrew Waterman	721770244e	Fix IBuf bug ... Don't examine a packet's xcpt signal if it might be invalid. In this case, the correct fix is to not examine xcpt at all; the deleted code was vestigial. (Note, the other use of xcpt(j+1) in this code is indeed safe.)	2017-08-09 09:47:51 -07:00
Yunsup Lee	fb2c22ca80	Merge pull request #944 from freechipsproject/fix-vlsi-mem-gen ... memgen: also randomize ren and rand register	2017-08-08 23:18:08 -07:00
Andrew Waterman	31b75987ca	Avoid width warning	2017-08-08 20:57:31 -07:00
Yunsup Lee	8705b0e070	memgen: also randomize ren and rand register	2017-08-08 20:41:53 -07:00
Richard Xia	97ad528a32	Merge pull request #941 from freechipsproject/bump-riscv-tools ... Bump riscv-tools to bump riscv-tests for mi-csr test fix.	2017-08-08 18:50:29 -07:00
Wesley W. Terpstra	49ba31ac34	Merge pull request #942 from freechipsproject/bus-blocker-lock ... Bus blocker lock	2017-08-08 18:03:36 -07:00
Wesley W. Terpstra	a9b1410f01	BusBlocker: parameterize page granularity	2017-08-08 17:10:01 -07:00
Wesley W. Terpstra	010ba94474	BusBlocker: rename a variable	2017-08-08 17:00:22 -07:00
Wesley W. Terpstra	6d6fc38787	BusBlocker: lock bit should affect the prior PMP address, not next	2017-08-08 17:00:12 -07:00
Richard Xia	dd5934b6dc	Bump riscv-tools to bump riscv-tests for mi-csr test fix and pull in stable binutils.	2017-08-08 16:29:26 -07:00
Yunsup Lee	0a351f677d	Merge pull request #940 from freechipsproject/fix-ecc-way ... Don't merge stores that manifest WAW hazards	2017-08-08 16:05:21 -07:00
Yunsup Lee	8cc41ab46b	Merge pull request #936 from freechipsproject/vlsi-mem-gen ... Improve and use vlsi_mem_gen for verilator flow	2017-08-08 16:04:53 -07:00
Andrew Waterman	809c7e8551	Don't merge stores that manifest WAW hazards ... The following sequence would drop the first store when eccBytes=4: sb x0, 0(t0) nop sb x0, 4(t0) nop sb x0, 1(t0) Because the first and second store are to different ECC granules, the hazard check correctly allowed the second one to proceed, but the third was merged with the second, even though it conflicted with the first. So, don't allow the third to be merged with the second, since the second stored to a different ECC granule.	2017-08-08 15:19:05 -07:00
Wesley W. Terpstra	3ef6e4c9f2	Merge pull request #939 from freechipsproject/bus-blocker ... tilelink: PMP controlled BusBlocker prevents bus accesses	2017-08-08 15:06:55 -07:00
Andrew Waterman	82e13443b2	Merge pull request #937 from freechipsproject/critical-paths ... Perform tag error detectoin/correction in same cycle as RAM	2017-08-08 15:03:28 -07:00
Andrew Waterman	dd103ae7ec	Merge pull request #938 from freechipsproject/dtim-ignore-cacheable ... Don't report to the DTIM that data is cacheable	2017-08-08 15:00:13 -07:00
Wesley W. Terpstra	8f261adc6b	BusBlocker: change default policy to deny	2017-08-08 14:19:59 -07:00
Wesley W. Terpstra	0d76e96b88	tilelink: PMP controlled BusBlocker prevents bus accesses	2017-08-08 13:28:01 -07:00
Andrew Waterman	7935c61c19	Don't report to the DTIM that data is cacheable ... Otherwise, it will attempt to perform AMOs where they're unsupported!	2017-08-08 11:55:04 -07:00
Andrew Waterman	74d309c18e	Make I vs. D a static property of TLB, not an input pin ... The microarchitecture doesn't really support unified TLBs, so don't fake it.	2017-08-08 11:54:47 -07:00
Andrew Waterman	e92981b0bd	DRY	2017-08-08 11:46:38 -07:00
Andrew Waterman	62ccba304c	Perform tag error detectoin/correction in same cycle as RAM ... The tag RAMs tend to be fast, so take up some of the slack. This makes s2_nack faster.	2017-08-08 10:21:30 -07:00
Palmer Dabbelt	6d1d285464	Merge pull request #933 from freechipsproject/cinst ... Print out the compressed instruction when executing one	2017-08-07 21:40:10 -07:00
Andrew Waterman	ea4b1bc349	Use vlsi_mem_gen for verilator flow	2017-08-07 20:36:22 -07:00
Andrew Waterman	b0f32c8f09	Randomize disabled read ports in vlsi_mem_gen	2017-08-07 20:35:40 -07:00
Palmer Dabbelt	cc1e2af336	Merge pull request #934 from freechipsproject/critical-paths ... Revert "Remove one gate from D$ ECC check"	2017-08-07 19:41:08 -07:00
Henry Cook	c8f8806df0	Merge pull request #932 from freechipsproject/tl-bus-delayer ... tilelink: allow insertion of TLDelayer on TLBus outward node	2017-08-07 19:01:39 -07:00
Henry Cook	c4092dd0cc	tilelink: improve entropy of bus delayer	2017-08-07 17:36:07 -07:00
Andrew Waterman	402907990c	Revert "Remove one gate from D$ ECC check" ... This reverts commit 7d94074b05, which works fine with optimistic behavioral RAMs but not real ones.	2017-08-07 17:33:20 -07:00
Henry Cook	2910d6fa2a	tilelink: make bus xbar protected so it can be suggestNamed	2017-08-07 17:30:24 -07:00
Palmer Dabbelt	fc0d5fcf98	Print out the compressed instruction when executing one	2017-08-07 17:21:53 -07:00
Wesley W. Terpstra	e27072e063	Merge pull request #931 from freechipsproject/fix-ram-model-source-reuse ... Fix ram model source reuse	2017-08-07 16:56:13 -07:00
Henry Cook	c457c9cb9f	tilelink: allow insertion of TLDelayer on TLBus outward node	2017-08-07 16:43:06 -07:00
Wesley W. Terpstra	d5a135914b	Revert "Disable AMBAUnitTestConfig, as it is blocking unrelated PRs" ... This reverts commit 39b7e930ca. Now that the RAMModel can properly tolerate overlapping responses in the face of source reuse, we can re-enable the regression test.	2017-08-07 16:04:02 -07:00
Yunsup Lee	03002b3106	Merge pull request #930 from freechipsproject/fix-maskrom ... maskrom: retain data for d channel is not ready	2017-08-07 16:01:38 -07:00
Wesley W. Terpstra	f8b45564d1	tilelink: RAMModel must support source reuse ... If a multibeat response comes back, the source might be reused. If response reordering has made the multibeat response invalid, we need to remember this even if the valid bit is cleared on reuse.	2017-08-07 16:01:15 -07:00
Yunsup Lee	558fc7f293	maskrom: retain data for d channel is not ready	2017-08-07 12:17:10 -07:00
Yunsup Lee	aff028f8f0	Merge pull request #926 from freechipsproject/bump-tools ... bump riscv-tools	2017-08-06 23:04:55 -07:00
Andrew Waterman	3d0051e799	bump tools for test fixes	2017-08-06 22:36:25 -07:00
Andrew Waterman	7fd8bb1159	Merge pull request #928 from freechipsproject/critical-paths ... Critical paths	2017-08-06 18:50:59 -07:00
Andrew Waterman	658e36f98b	Reduce fanout on frontend io.cpu.req.valid signal	2017-08-06 17:38:51 -07:00
Andrew Waterman	7d94074b05	Remove one gate from D$ ECC check ... The D$ corrects via writeback, so which word the error was in doesn't matter, as the entire line is corrected.	2017-08-06 17:36:53 -07:00
Wesley W. Terpstra	d03fdc4f30	diplomacy: seal the LazyModuleImpLike trait (#927) ... This makes sure that all the base classes call instantiate()	2017-08-06 17:32:23 -07:00
Yunsup Lee	5030a8b15a	Merge pull request #925 from freechipsproject/fix-lazy-raw-modules ... diplomacy: provide default clock/reset for LazyRawModuleImp	2017-08-06 14:42:14 -07:00
Yunsup Lee	aa60c6944b	diplomacy: provide default clock/reset for LazyRawModuleImp	2017-08-06 13:40:07 -07:00
Yunsup Lee	6389120dbd	Merge pull request #923 from freechipsproject/critical-paths ... Critical paths	2017-08-05 17:02:22 -07:00
Andrew Waterman	39b7e930ca	Disable AMBAUnitTestConfig, as it is blocking unrelated PRs	2017-08-05 16:14:02 -07:00
Andrew Waterman	83875e3a0c	Only flush D$ on FENCE.I if it won't always be probed on I$ miss	2017-08-05 14:22:40 -07:00
Andrew Waterman	991e16de92	Remove probe address mux from TLB response path	2017-08-05 12:57:38 -07:00
Andrew Waterman	b9b4142bb4	Get s2_nack off the critical path ... We were using it to compute the next PC on flush vs. replay (which require PC+4 and PC, respectively). This fix gets rid of the adder altogether by reusing the M-stage PC in the flush case, which by construction holds PC+4.	2017-08-05 00:30:36 -07:00