Andrew Waterman
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bc298bf146
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Optimize ShiftQueue for late-arriving deq.ready
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2017-08-04 22:06:37 -07:00 |
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Andrew Waterman
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6112adfbb0
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Get L2 TLB tag/parity check off the D$ arbitration path
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2017-08-04 17:01:51 -07:00 |
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Andrew Waterman
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8d97684555
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Fix L2 TLB perfctr
It was counting conflict misses but not cold misses.
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2017-08-04 17:01:31 -07:00 |
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Andrew Waterman
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df7f09b9ce
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Get I$ ECC check further off critical path
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2017-08-04 16:59:21 -07:00 |
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Andrew Waterman
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4bfbe75d74
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Avoid pipeline replays when fetch queue is full
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2017-08-04 16:59:21 -07:00 |
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Andrew Waterman
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a45997d03f
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Separate I$ parity error from miss signal
Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
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2017-08-04 16:59:21 -07:00 |
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Andrew Waterman
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06a831310b
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Shave a gate delay off I$ backpressure path
The deleted code was a holdover from Hwacha's vector fences.
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2017-08-04 13:12:43 -07:00 |
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Andrew Waterman
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ecc2ee366c
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Shave a few gate delays off IBuf control logic
It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.
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2017-08-04 13:12:43 -07:00 |
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Andrew Waterman
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82ff81e40d
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Merge pull request #924 from freechipsproject/dont-build-debug-verilog
Don't build verilog twice for emulator and emulator-debug
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2017-08-04 10:16:59 -07:00 |
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Andrew Waterman
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7937db0c84
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Merge pull request #919 from freechipsproject/imiss-perf-counter
Fix I$ miss perfctr
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2017-08-04 01:04:23 -07:00 |
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Andrew Waterman
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21ac28b57a
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Don't build verilog twice for emulator and emulator-debug
Since we aren't using chisel2, the output is the same either way.
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2017-08-04 01:02:33 -07:00 |
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Megan Wachs
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017ac130c1
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Merge pull request #922 from freechipsproject/bigger_tl_xbar
TLXbar: Allow more masters and slaves and issue a warning.
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2017-08-03 16:52:56 -07:00 |
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Megan Wachs
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50c85f1b62
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TLXbar: Allow more masters and slaves and issue a warning.
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2017-08-03 15:46:06 -07:00 |
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Andrew Waterman
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ba4eecc0f0
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Use UIntToOH1 (#921)
Closes #920
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2017-08-03 14:55:39 -07:00 |
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Andrew Waterman
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f483bab4aa
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Fix I$ miss perfctr
The old version was counting prefetches, too.
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2017-08-03 00:52:12 -07:00 |
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Andrew Waterman
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1be1433f04
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Merge pull request #918 from freechipsproject/icache-prefetch
Icache prefetch
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2017-08-02 21:22:20 -07:00 |
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Andrew Waterman
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d66e8f8e80
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Merge pull request #914 from freechipsproject/critical-paths
Fix some critical paths
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2017-08-02 19:05:31 -07:00 |
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Megan Wachs
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3fc7100048
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Merge pull request #917 from freechipsproject/fuzzer_order
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
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2017-08-02 18:39:59 -07:00 |
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Andrew Waterman
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2537d0d54e
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Optionally prefetch next I$ line into L2$ on miss
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2017-08-02 17:10:56 -07:00 |
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Andrew Waterman
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744cdb2f72
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Make TLB report when it's safe to prefetch within a page
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2017-08-02 17:09:38 -07:00 |
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Megan Wachs
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d9821a74ce
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Merge pull request #916 from freechipsproject/transfer_sizes_print
diplomacy: Pretty Print for TransferSizes
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2017-08-02 16:56:36 -07:00 |
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Megan Wachs
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595415d207
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TLFuzzer: Correct the number of ordered clients created
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2017-08-02 15:48:21 -07:00 |
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Megan Wachs
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fc5c04ed4b
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TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
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2017-08-02 14:44:18 -07:00 |
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Andrew Waterman
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7d2dd3769f
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Optimize a hazard check critical path
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2017-08-02 14:27:25 -07:00 |
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Megan Wachs
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85bdae0fa8
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diplomacy: Pretty Print for TransferSizes
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2017-08-02 11:40:50 -07:00 |
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Andrew Waterman
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2eb239d03f
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Add option to retime D$ way mux into subsequent pipeline stage
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2017-08-01 23:59:20 -07:00 |
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Andrew Waterman
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9464c6db40
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Mitigate(?) frontend critical path
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2017-08-01 18:51:17 -07:00 |
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Andrew Waterman
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735701382f
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Mitigate some I$ response valid critical paths
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2017-08-01 18:51:17 -07:00 |
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Andrew Waterman
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2ecea2ef60
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Don't use a pipe queue on D$ TL A-channel
This cuts an I$->D$ path.
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2017-08-01 15:17:07 -07:00 |
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Yunsup Lee
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f988b91575
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Merge pull request #912 from freechipsproject/add-mask-rom
tilelink: add mask rom
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2017-07-31 22:28:11 -07:00 |
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Yunsup Lee
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6ef8ee5d4d
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tilelink: add mask rom
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2017-07-31 21:34:04 -07:00 |
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Yunsup Lee
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4b33249812
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Merge pull request #911 from freechipsproject/fix-dcache-bug
Fix D$ ready-valid signaling bug
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2017-07-31 19:14:16 -07:00 |
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Wesley W. Terpstra
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42ff74bd34
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Merge pull request #910 from freechipsproject/tilelink-map
Tilelink map
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2017-07-31 18:33:09 -07:00 |
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Andrew Waterman
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e140893a01
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Use 1-entry queue on processor-side E-channel
The cache can't sink a grant every cycle, so extra E buffering doesn't help.
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2017-07-31 18:06:54 -07:00 |
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Andrew Waterman
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5681693ccc
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Fix a D$ ready-valid signaling regression
I broke this in 66d06460fa.
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2017-07-31 18:05:14 -07:00 |
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Wesley W. Terpstra
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d7fd9d2b82
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tilelink: Filter, add another case
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2017-07-31 16:51:26 -07:00 |
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Yunsup Lee
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71a250b071
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Merge pull request #909 from freechipsproject/tile-buffer
add optional tile boundary buffers
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2017-07-31 16:46:22 -07:00 |
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Wesley W. Terpstra
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b126105230
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tilelink: add TLMap to make it possible to move slaves
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2017-07-31 16:39:00 -07:00 |
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Wesley W. Terpstra
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13d3ffbcaa
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tilelink: Filter now support arbitrary filter functions
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2017-07-31 16:38:38 -07:00 |
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Yunsup Lee
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7adfd5c431
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Merge pull request #906 from freechipsproject/critical-paths
Mitigate I$->D$->I$ critical path
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2017-07-31 16:14:11 -07:00 |
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Megan Wachs
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07b4edfc87
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Merge pull request #908 from freechipsproject/combo-breaker
dcache: break potential combinatorial loop
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2017-07-31 16:13:01 -07:00 |
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Yunsup Lee
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f473e6bad0
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tile: add optional boundary buffers
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2017-07-31 15:57:22 -07:00 |
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Yunsup Lee
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cb3529bbc3
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util: tweak rational crossings to avoid mux in source
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2017-07-31 15:10:15 -07:00 |
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Henry Cook
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11332c1226
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dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative
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2017-07-31 14:03:30 -07:00 |
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Andrew Waterman
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d811692c3b
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Mitigate I$->D$->I$ critical path
This seemingly irrelevant change shaves several gate delays off the I$
tl.a.valid path.
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2017-07-31 01:43:04 -07:00 |
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Yunsup Lee
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ea1840c4b1
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Merge pull request #904 from freechipsproject/fix-dcache-bug
Fix D$ ready-valid signaling bug
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2017-07-29 20:30:47 -07:00 |
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Andrew Waterman
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ac4339a8e7
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Pass D$ backpressure to D-channel, rather than asserting
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2017-07-29 11:48:36 -07:00 |
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Andrew Waterman
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edcd2c696c
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Avoid needless stall on E-channel back pressure
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2017-07-29 11:47:58 -07:00 |
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Wesley W. Terpstra
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8e2e931770
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Merge pull request #903 from freechipsproject/monitor-probes
tilelink: use the Monitor to enforce Probe sourcing
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2017-07-29 01:12:08 -07:00 |
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Wesley W. Terpstra
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56e28026a6
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TLError: does not need to be fast; cut the loop
The SystemBus already has a flow buffer on outputs.
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2017-07-29 00:22:21 -07:00 |
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