Andrew Waterman
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6c0e1e33ab
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Purge UInt := SInt assignments
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2015-07-31 15:42:10 -07:00 |
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Andrew Waterman
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049fc8dc24
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Chisel3 compatibility: use BitPat for don't-cares
This one's hella ugly, but for the time being, idgaf.
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2015-07-28 02:48:49 -07:00 |
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Henry Cook
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741e6b77ad
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Rename some params, use refactored TileLink
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2015-02-01 20:37:31 -08:00 |
|
Yunsup Lee
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8abf62fae3
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add LICENSE
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2014-09-12 18:06:41 -07:00 |
|
Henry Cook
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b42a2ab40a
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Final parameter refactor
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2014-09-01 13:28:58 -07:00 |
|
Henry Cook
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0dac9a7467
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Full conversion to params. Compiles but does not elaborate.
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2014-08-19 11:38:02 -07:00 |
|
Andrew Waterman
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4ca152b012
|
Use BundleWithConf to avoid clone method boilerplate
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2014-05-09 19:37:16 -07:00 |
|
Andrew Waterman
|
09e2ec1f9e
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Fix sign of remainder when dividing by zero
h/t chris
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2014-04-18 16:32:57 -07:00 |
|
Andrew Waterman
|
3ed8adf032
|
Add early out for MUL[W] (not MULH[[S]U])
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2014-04-07 23:48:02 -07:00 |
|
Andrew Waterman
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a50a1f7d50
|
Clean up multiplier/divider stuff
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2014-01-13 21:37:16 -08:00 |
|
Henry Cook
|
3a266cbbfa
|
final Reg changes
|
2013-08-15 15:28:15 -07:00 |
|
Henry Cook
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1a9e43aa11
|
initial attempt at upgrade
|
2013-08-12 10:39:11 -07:00 |
|
Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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Andrew Waterman
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29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Yunsup Lee
|
ee081d1671
|
modify code to fix UFix := Bits error
|
2012-11-05 01:35:55 -08:00 |
|
Andrew Waterman
|
7380c9fe60
|
aggressively clock gate int and fp datapaths
|
2012-11-04 16:40:14 -08:00 |
|
Andrew Waterman
|
661f8e635b
|
merge I$, ITLB, BTB into Frontend
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
fcd69dba98
|
add optional early-out to mul/div
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
27ddff1adb
|
simplify and improve multiplier
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
0f20771664
|
rename queue to Queue
fixes build with case-insensitive file system
|
2012-08-08 22:11:59 -07:00 |
|
Huy Vo
|
fd95159837
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
Huy Vo
|
04304fe788
|
moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
Yunsup Lee
|
8678b3d70c
|
clean up ioDecoupled/ioPipe interface
|
2012-03-01 20:48:46 -08:00 |
|
Yunsup Lee
|
94ba32bbd3
|
change package name and sbt project name to rocket
|
2012-02-25 17:09:26 -08:00 |
|
Yunsup Lee
|
3839e3a318
|
massive refactoring of vector constants
|
2012-02-25 15:55:36 -08:00 |
|
Andrew Waterman
|
4121fb178c
|
clean up mul/div interface; use VU mul if HAVE_VEC
|
2012-02-24 19:22:35 -08:00 |
|
Andrew Waterman
|
725190d0ee
|
update to new chisel
|
2012-02-11 17:20:33 -08:00 |
|
Andrew Waterman
|
92493ad153
|
fix mul/div kill bug
occasionally, an in-progress multiply or divide could be
erroneously killed, tying up the register forever.
|
2012-02-09 02:26:03 -08:00 |
|
Henry Cook
|
1d76255dc1
|
new chisel version jar and find and replace INPUT and OUTPUT
|
2012-01-18 14:39:57 -08:00 |
|
Andrew Waterman
|
20aee36c96
|
move PCR writes to WB stage
|
2012-01-02 15:42:39 -08:00 |
|
Andrew Waterman
|
1028ff7d9b
|
fix multiplier bug
|
2011-12-29 23:45:09 -08:00 |
|
Andrew Waterman
|
38ea10a5f4
|
parameterized multiplier unrolling
|
2011-12-20 04:18:28 -08:00 |
|
Andrew Waterman
|
733fc8e65e
|
booth multiplier
|
2011-12-20 03:49:07 -08:00 |
|
Andrew Waterman
|
bcceb08373
|
add dummy mul_rdy signal
|
2011-12-17 07:30:47 -08:00 |
|
Andrew Waterman
|
82700cad72
|
fix multiplier for rv32
|
2011-12-17 07:20:00 -08:00 |
|
Rimas Avizienis
|
c06e2d16e4
|
initial commit of rocket chisel project, riscv assembly tests and benchmarks
|
2011-10-25 23:02:47 -07:00 |
|