150 lines
4.5 KiB
Scala
150 lines
4.5 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import Constants._
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import hwacha._
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import hwacha.Constants._
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class ioMultiplier extends Bundle {
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val req = new io_imul_req().flip
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val req_tag = Bits(5, INPUT)
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val req_kill = Bool(INPUT)
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val resp_val = Bool(OUTPUT)
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val resp_rdy = Bool(INPUT)
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val resp_tag = Bits(5, OUTPUT)
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val resp_bits = Bits(SZ_XLEN, OUTPUT)
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}
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class rocketVUMultiplier(nwbq: Int) extends Component {
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val io = new Bundle {
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val cpu = new ioMultiplier
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val vu = new Bundle {
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val req = new io_imul_req
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val resp = Bits(SZ_XLEN, INPUT)
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}
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}
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val valid = Reg(resetVal = Bits(0, IMUL_STAGES))
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val wbq_cnt = Reg(resetVal = Bits(0, log2up(nwbq+1)))
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val tag = Vec(IMUL_STAGES) { Reg() { Bits() } }
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val fire = io.cpu.req.valid && io.cpu.req.ready
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valid := Cat(fire, valid(IMUL_STAGES-1) && !io.cpu.req_kill, valid(IMUL_STAGES-2,1))
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when (fire) {
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tag(IMUL_STAGES-1) := io.cpu.req_tag
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}
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for (i <- 0 until IMUL_STAGES-1) {
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tag(i) := tag(i+1)
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}
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when (valid(0) != (io.cpu.resp_val && io.cpu.resp_rdy)) {
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wbq_cnt := Mux(valid(0), wbq_cnt + UFix(1), wbq_cnt - UFix(1))
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}
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var inflight_cnt = valid(0)
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for (i <- 1 until IMUL_STAGES)
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inflight_cnt = inflight_cnt + valid(i)
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inflight_cnt = inflight_cnt + wbq_cnt
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val wbq_rdy = inflight_cnt < UFix(nwbq)
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val wbq = (new queue(nwbq)) { Bits(width = io.cpu.resp_bits.width + io.cpu.resp_tag.width) }
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wbq.io.enq.valid := valid(0)
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wbq.io.enq.bits := Cat(io.vu.resp, tag(0))
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wbq.io.deq.ready := io.cpu.resp_rdy
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io.cpu.req.ready := io.vu.req.ready && wbq_rdy
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io.cpu.resp_val := wbq.io.deq.valid
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io.cpu.resp_bits := wbq.io.deq.bits >> UFix(io.cpu.resp_tag.width)
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io.cpu.resp_tag := wbq.io.deq.bits(io.cpu.resp_tag.width-1,0)
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io.vu.req <> io.cpu.req
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}
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class rocketMultiplier extends Component {
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val io = new ioMultiplier
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// w must be even (booth).
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// we need an extra bit to handle signed vs. unsigned,
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// so we need to add a second to keep w even.
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val w = 64 + 2
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val unroll = 3
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require(w % 2 == 0 && (w/2) % unroll == 0)
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val cycles = w/unroll/2
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val r_val = Reg(resetVal = Bool(false));
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val r_dw = Reg { Bits() }
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val r_fn = Reg { Bits() }
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val r_tag = Reg { Bits() }
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val r_lhs = Reg { Bits() }
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val r_prod= Reg { Bits(width = w*2) }
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val r_lsb = Reg { Bits() }
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val r_cnt = Reg { UFix(width = log2up(cycles+1)) }
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val dw = io.req.bits.fn(io.req.bits.fn.width-1)
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val fn = io.req.bits.fn(io.req.bits.fn.width-2,0)
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val lhs_msb = Mux(dw === DW_64, io.req.bits.in0(63), io.req.bits.in0(31)).toBool
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val lhs_sign = ((fn === MUL_H) || (fn === MUL_HSU)) && lhs_msb
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val lhs_hi = Mux(dw === DW_64, io.req.bits.in0(63,32), Fill(32, lhs_sign))
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val lhs_in = Cat(lhs_sign, lhs_hi, io.req.bits.in0(31,0))
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val rhs_msb = Mux(dw === DW_64, io.req.bits.in1(63), io.req.bits.in1(31)).toBool
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val rhs_sign = (fn === MUL_H) && rhs_msb
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val rhs_hi = Mux(dw === DW_64, io.req.bits.in1(63,32), Fill(32, rhs_sign))
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val rhs_in = Cat(rhs_sign, rhs_sign, rhs_hi, io.req.bits.in1(31,0))
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val do_kill = io.req_kill && r_cnt === UFix(0) // can only kill on 1st cycle
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when (io.req.valid && io.req.ready) {
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r_val := Bool(true)
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r_cnt := UFix(0, log2up(cycles+1))
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r_dw := dw
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r_fn := fn
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r_tag := io.req_tag
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r_lhs := lhs_in
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r_prod:= rhs_in
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r_lsb := Bool(false)
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}
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.elsewhen (io.resp_val && io.resp_rdy || do_kill) { // can only kill on first cycle
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r_val := Bool(false)
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}
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val lhs_sext = Cat(r_lhs(w-2), r_lhs(w-2), r_lhs).toUFix
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val lhs_twice = Cat(r_lhs(w-2), r_lhs, Bits(0,1)).toUFix
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var prod = r_prod
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var lsb = r_lsb
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for (i <- 0 until unroll) {
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val addend = Mux(prod(0) != lsb, lhs_sext,
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Mux(prod(0) != prod(1), lhs_twice,
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UFix(0)));
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val sub = prod(1)
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val adder_lhs = Cat(prod(w*2-1), prod(w*2-1,w)).toUFix
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val adder_rhs = Mux(sub, ~addend, addend)
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val adder_out = (adder_lhs + adder_rhs + sub.toUFix)(w,0)
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lsb = prod(1)
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prod = Cat(adder_out(w), adder_out, prod(w-1,2))
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}
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when (r_val && (r_cnt != UFix(cycles))) {
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r_lsb := lsb
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r_prod := prod
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r_cnt := r_cnt + UFix(1)
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}
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val mul_output64 = Mux(r_fn === MUL_LO, r_prod(63,0), r_prod(127,64))
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val mul_output32 = Mux(r_fn === MUL_LO, r_prod(31,0), r_prod(63,32))
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val mul_output32_ext = Cat(Fill(32, mul_output32(31)), mul_output32)
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val mul_output = Mux(r_dw === DW_64, mul_output64, mul_output32_ext)
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io.req.ready := !r_val
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io.resp_bits := mul_output;
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io.resp_tag := r_tag;
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io.resp_val := r_val && (r_cnt === UFix(cycles))
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}
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