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Commit Graph

537 Commits

Author SHA1 Message Date
Andrew Waterman
64674d4d39 clean up PTW and support PADDR_BITS < VADDR_BITS 2012-11-26 20:38:45 -08:00
Andrew Waterman
608f65e716 don't wastefully read 2x the bits from D$ RAMs 2012-11-26 20:34:30 -08:00
Andrew Waterman
352bb464b5 clock gate X/M and M/W store data registers 2012-11-26 20:33:41 -08:00
Andrew Waterman
8a6ff5f9aa fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
2012-11-25 19:46:48 -08:00
Andrew Waterman
de2f28193a get rid of more global constants 2012-11-25 04:24:25 -08:00
Andrew Waterman
c036cdc1ea add option for 2-cycle load-use delay 2012-11-24 22:01:08 -08:00
Andrew Waterman
b514c7b725 clean up I$ parity code 2012-11-24 22:00:43 -08:00
Andrew Waterman
55082e45c4 add AVec, which automatically infers element type
should consider modifying Vec as such
2012-11-24 18:19:28 -08:00
Andrew Waterman
2b26082132 use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
2012-11-20 04:09:26 -08:00
Andrew Waterman
72f94d1141 fix virtual address sign extension detection 2012-11-20 04:06:57 -08:00
Andrew Waterman
30038bda8a bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
2012-11-20 01:33:32 -08:00
Yunsup Lee
395e4e3dd6 andrew'x fix for D$ corner case in writeback->abort->probe 2012-11-18 03:11:06 -08:00
Yunsup Lee
06eeb90e2a vector unit interfaces to the new D$ 2012-11-17 20:07:41 -08:00
Yunsup Lee
81d711e892 fix D$ bug; now D$ doesn't respond to prefetches 2012-11-17 20:06:13 -08:00
Andrew Waterman
29bc361d6c remove global constants; disentangle hwacha a bit 2012-11-17 17:24:08 -08:00
Andrew Waterman
5a7777fe4d clock gate integer datapath more aggressively 2012-11-17 06:48:44 -08:00
Andrew Waterman
cc067026a2 pipeline D$ response -> FPU regfile 2012-11-17 06:48:11 -08:00
Andrew Waterman
e68b039133 fix misc. D$ control bugs 2012-11-17 06:47:27 -08:00
Andrew Waterman
dad7b71062 provide cmd/addr with cache response 2012-11-16 21:26:12 -08:00
Andrew Waterman
cb8ac73045 provide store data with cache response 2012-11-16 21:15:13 -08:00
Andrew Waterman
9e010beffe fix D$ refill bug 2012-11-16 21:05:29 -08:00
Andrew Waterman
8dce89703a new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
2012-11-16 02:39:33 -08:00
Andrew Waterman
a90a1790a5 improve tlb qor 2012-11-16 01:59:38 -08:00
Andrew Waterman
ff8c736d94 move icache invalidate out of request bundle 2012-11-16 01:55:45 -08:00
Andrew Waterman
6d10115b19 fix D$ tag width 2012-11-15 16:46:39 -08:00
Yunsup Lee
be1980dd2d refactored vector queue interface 2012-11-07 01:15:33 -08:00
Yunsup Lee
8764fe786a refactored vector tlb 2012-11-06 23:53:52 -08:00
Yunsup Lee
9a02298f6f andrew's fix for tlb lockup 2012-11-06 23:52:58 -08:00
Andrew Waterman
4d1ca8ba3a remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
2012-11-06 08:13:44 -08:00
Andrew Waterman
e76892f758 remove more global constants 2012-11-06 02:55:45 -08:00
Andrew Waterman
c5b93798fb factor out more global constants 2012-11-05 23:52:32 -08:00
Yunsup Lee
ee081d1671 modify code to fix UFix := Bits error 2012-11-05 01:35:55 -08:00
Yunsup Lee
2a25307a8f revamp the vector unit with the new frontend 2012-11-05 01:35:55 -08:00
Andrew Waterman
5b20ed71be move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
2012-11-05 01:30:57 -08:00
Andrew Waterman
5e103054fd fix bug in quine mccluskey 2012-11-05 00:28:25 -08:00
Andrew Waterman
e9eca6a95d refactor I$ config; remove Top class 2012-11-04 16:59:36 -08:00
Andrew Waterman
7380c9fe60 aggressively clock gate int and fp datapaths 2012-11-04 16:40:14 -08:00
Andrew Waterman
bd2d61de03 use 8T SRAM for I$; gate clock more aggressively 2012-11-04 16:39:25 -08:00
Andrew Waterman
fedee6c67d add generic error correcting codes 2012-10-30 01:03:47 -07:00
Andrew Waterman
5773cbb68a rejigger htif to use UncoreConfiguration 2012-10-18 17:26:03 -07:00
Henry Cook
e2eb7ce8e9 Cleanup git incompetence 2012-10-16 16:54:58 -07:00
Henry Cook
88ac5af181 Merged consts-as-traits 2012-10-16 16:32:35 -07:00
Henry Cook
6cff1c13d8 Refer to traits moved to uncore, add UncoreConfiguration to top 2012-10-16 14:22:23 -07:00
Andrew Waterman
b9a2af697d turn off HAVE_VEC as it's currently broken
the new I$/frontend needs to be integrated
2012-10-16 07:38:19 -07:00
Andrew Waterman
0a640f2cc6 make DecodeLogic deterministic (hopefully) 2012-10-16 04:51:21 -07:00
Andrew Waterman
5821900329 don't refetch from I$ if on same 16B block 2012-10-16 02:24:38 -07:00
Andrew Waterman
b955985b38 improve divider QoR 2012-10-16 02:24:38 -07:00
Andrew Waterman
197154c485 use BTB for JALR 2012-10-16 02:24:37 -07:00
Andrew Waterman
fc648d13a1 remove old Mux1H; add implicit conversions 2012-10-16 02:24:37 -07:00
Andrew Waterman
661f8e635b merge I$, ITLB, BTB into Frontend 2012-10-16 02:24:37 -07:00