riscv/rocket-chip
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532 Commits

Author SHA1 Message Date
Stephen Twigg
3b3250339a Explicitely convert results of Bits Muxes to UInt 
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
 2015-02-03 18:15:01 -08:00
Henry Cook
57340be72b doc update 2015-02-02 01:11:13 -08:00
Henry Cook
6141b3efc5 uncached -> builtin_type 2015-02-02 01:02:06 -08:00
Henry Cook
e6491d351f Offset AMOs within beat and return old value 2015-02-02 00:22:21 -08:00
Henry Cook
3aa030f960 Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor. 2015-02-01 20:37:16 -08:00
Henry Cook
7b4e9dd137 Block L2 transactions on the same set from proceeding in parallel 2015-02-01 20:29:23 -08:00
Henry Cook
973eb43128 state machine bug on uncached write hits 2015-02-01 20:29:23 -08:00
Henry Cook
f58f8bf385 Make L2 data array use a single Mem 2015-01-25 15:37:04 -08:00
Henry Cook
9ef00d187f %s/master/manager/g + better comments 2014-12-29 22:55:58 -08:00
Henry Cook
c76b4bc21d TileLink doc 2014-12-29 22:55:18 -08:00
Henry Cook
e62c71203e disconnect unused outer network headers 2014-12-22 18:50:37 -08:00
Henry Cook
2ef4357ca8 acquire allocation bugfix 2014-12-19 17:39:23 -08:00
Henry Cook
f234fe65ce Initial verison of L2WritebackUnit, passes MiT2 bmark tests 2014-12-19 03:03:53 -08:00
Henry Cook
d121af7f94 Simplify release handling 2014-12-18 17:12:29 -08:00
Henry Cook
bfcfc3fe18 refactor cache params 2014-12-17 14:28:14 -08:00
Henry Cook
ab39cbb15d cleanup DirectoryRepresentation and coherence params 2014-12-15 19:24:42 -08:00
Andrew Waterman
d04da83f96 Make data RAMs 1RW instead of 1R1W 2014-12-15 17:36:17 -08:00
Henry Cook
6a8b66231c Add uncached->cached tilelink converter 2014-12-12 17:06:03 -08:00
Henry Cook
424df2368f 1R/W L2 data array? 
Add TLDataBeats to new LLC; all bmarks pass
 2014-12-12 17:05:21 -08:00
Henry Cook
3026c46a9c Finish adding TLDataBeats to uncore & hub 2014-12-12 17:04:52 -08:00
Henry Cook
2f733a60db Begin adding TLDataBeats to uncore 2014-12-12 17:04:31 -08:00
Henry Cook
404773eb9f fix wb bug 2014-12-03 14:22:39 -08:00
Henry Cook
05b5188ad9 meta and data bundle refactor 2014-11-19 15:55:25 -08:00
Henry Cook
a519a43f23 Merge branch 'master' into new-llc 
Conflicts:
	src/main/scala/coherence.scala
	src/main/scala/memserdes.scala
	src/main/scala/tilelink.scala
 2014-11-12 16:25:25 -08:00
Henry Cook
cb7e712599 Added uncached write data queue to coherence hub 2014-11-12 12:55:07 -08:00
Henry Cook
82155f333e Major tilelink revision for uncached message types 2014-11-11 17:36:55 -08:00
Henry Cook
35553cc0b7 NullDirectory sharers.count fix 2014-11-11 16:05:25 -08:00
Henry Cook
10309849b7 Remove master_xact_id from Probe and Release 2014-11-06 12:07:33 -08:00
Henry Cook
27c72e5eed nearly all isa tests pass 2014-10-23 21:50:03 -07:00
Henry Cook
a891ba1d46 more correct handling of internal state 2014-10-21 17:40:30 -07:00
Henry Cook
044b19dbc1 Compiles and elaborates, does not pass asm tests 2014-10-15 11:46:35 -07:00
Henry Cook
86bdbd6535 new tshrs, compiles but does not elaborate 2014-10-07 22:33:10 -07:00
Henry Cook
394eb38a96 temp; converted voluntary wb tracker 2014-10-03 01:06:49 -07:00
Henry Cook
dc1a61264d initial version, acts like old hub 2014-10-03 01:06:49 -07:00
Henry Cook
d735f64110 Parameter API update 2014-10-02 16:47:35 -07:00
Henry Cook
7571695320 Removed broken or unfinished modules, new MemPipeIO converter 2014-09-24 15:11:24 -07:00
Henry Cook
82fe22f958 support for multiple tilelink paramerterizations in same design 
Conflicts:

	src/main/scala/cache.scala
 2014-09-24 11:30:40 -07:00
Henry Cook
53b8d7b031 use new coherence methods in l2, ready to query dir logic 2014-09-20 18:01:14 -07:00
Henry Cook
149d51d644 more coherence API cleanup 2014-09-20 16:57:13 -07:00
Henry Cook
faed47d131 use thunk for dir info 2014-09-20 16:54:28 -07:00
Henry Cook
f7b1e23ead functional style on MuxBundle 2014-09-20 16:54:28 -07:00
Yunsup Lee
f249da1803 update README 2014-09-17 11:25:14 -07:00
Yunsup Lee
49b027db2c forgot to add LICENSE file 2014-09-12 15:36:29 -07:00
Yunsup Lee
0b51d70bd2 add LICENSE 2014-09-12 15:31:38 -07:00
Yunsup Lee
f8d450b4e2 mark DRAMSideLLC as HasKnownBug 2014-09-11 22:06:03 -07:00
Henry Cook
5e26b4ab66 Merge branch 'dse' 
Conflicts:
	src/main/scala/htif.scala
	src/main/scala/llc.scala
 2014-09-06 06:16:58 -07:00
Scott Beamer
f8821b4cc9 better fix with explanation of sbt issue 2014-09-02 15:16:03 -07:00
Scott Beamer
bfb662968d fixes sbt error during first run 2014-09-02 14:33:58 -07:00
Henry Cook
712f3a754d merge in master 2014-09-02 12:34:42 -07:00
Henry Cook
17b2359c9a htif parameters trait 2014-08-24 19:27:58 -07:00
Henry Cook
dc5643b12f Final parameter refactor. 2014-08-23 01:19:36 -07:00
Scott Beamer
e384b33cc3 don't generate a write mask for BigMem if it isn't used 
not needed for llc data
 2014-08-19 15:50:20 -07:00
Henry Cook
e26f8a6f6a Fix errors in derived cache params 2014-08-12 14:55:44 -07:00
Henry Cook
9ab3a4262c Cache utility traits. Completely compiles, asm tests hang. 2014-08-11 18:35:49 -07:00
Henry Cook
f411fdcce3 Full conversion to params. Compiles but does not elaborate. 2014-08-08 12:21:57 -07:00
Jim Lawson
0020ded367 Replace needWidth() with getWidth. 2014-06-13 14:53:48 -07:00
Jim Lawson
a04ef4f5f4 Quick change to work with new Width class. 
Replace .width with .needWidth()
 2014-06-13 11:44:43 -07:00
Andrew Waterman
1ae7a9376c Fix unhandled LLC writeback hazard 2014-06-13 03:25:52 -07:00
Henry Cook
3c329df7e7 refactor Metadata, clean and expand coherence API 2014-05-28 13:35:08 -07:00
Andrew Waterman
364a6de214 Use Mem instead of Vec[Reg] 2014-05-18 19:26:35 -07:00
Henry Cook
0e39346a12 L2-specific metadataarray wrapper, hookups to tshrfile 2014-05-07 01:51:46 -07:00
Henry Cook
bc3ef1011e correct use of function value to initialize MetaDataArray 2014-05-06 12:59:45 -07:00
Henry Cook
45172f1f37 parameterize metadataarray 2014-05-01 01:44:59 -07:00
Henry Cook
0237229921 client/master -> inner/outer 2014-04-29 16:49:18 -07:00
Henry Cook
52c6de5641 DRAMSideLLCLike trait. TSHRFile. New L2 config objects. 2014-04-26 19:11:36 -07:00
Henry Cook
1163131d1e TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:17:05 -07:00
Henry Cook
3f53d532c2 uniquify tilelink conf val name for easier subtyping 2014-04-26 14:58:38 -07:00
Henry Cook
f8f29c69b8 MetaData & friends moved to uncore/ 2014-04-23 16:24:20 -07:00
Henry Cook
39681303b8 beginning of l2 cache 2014-04-22 16:58:15 -07:00
Henry Cook
5613dc7d1b replaced Lists with Vecs 2014-04-18 17:26:56 -07:00
Jim Lawson
bf2ff7804e Add chisel-dependent.sbt for -DchiselVersion="latest.release" 
If -DchiselVersion is specified on the command line, add the
appropriate chisel library to libraryDependencies.
 2014-04-17 17:01:40 -07:00
Henry Cook
b1df49ba30 removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants 2014-04-10 12:35:43 -07:00
Henry Cook
fbca7c6bb3 refactor ioMem and associcated constants. merge Aqcuire and AcquireData 2014-04-10 12:35:43 -07:00
Jim Lawson
a228dbfa0d Revert "Update library dependencies (jenkins builds)" 
This reverts commit e7a12143d0bfe8b3b4a4dcc78d119a89553ade8c.
 2014-03-20 10:40:05 -07:00
Jim Lawson
dec98eb047 Update library dependencies (jenkins builds) 
Add chisel as an explicit library dependency
 2014-03-18 11:37:08 -07:00
Andrew Waterman
02dbd6b0aa Don't assign to your own inputs 2014-02-12 18:39:40 -08:00
Henry Cook
bbf8010230 cleanups supporting uncore hierarchy 2014-01-31 15:59:21 -08:00
Andrew Waterman
3e634aef1d Fix HTIF for cache line sizes other than 64 B 2014-01-22 18:20:36 -08:00
Andrew Waterman
4f1213cb8b Fix Scala integer overflow 2014-01-13 21:45:14 -08:00
Andrew Waterman
acc0d2b06c Only use LSBs for HTIF control regs 
For now, at least...
 2013-11-25 04:34:16 -08:00
Yunsup Lee
056bb156ca make CacheConstants an object 2013-11-20 16:43:55 -08:00
Yunsup Lee
f13d76628b forgot to put htif into uncore package 2013-11-07 15:42:10 -08:00
Yunsup Lee
c350cbd6ea move htif to uncore 2013-11-07 13:19:04 -08:00
Yunsup Lee
f440df5338 rename M_FENCE to M_NOP 2013-10-28 22:37:41 -07:00
Henry Cook
42693d43ad simplify build.sbt 2013-09-26 09:51:14 -07:00
Stephen Twigg
20246b373e Properly ignore target files 2013-09-24 16:02:00 -07:00
Huy Vo
cc3dc1bd0f bug fix 2013-09-19 20:10:56 -07:00
Andrew Waterman
cc7783404d Add memory command M_XA_XOR 2013-09-12 16:09:53 -07:00
Henry Cook
1cac26fd76 NetworkIOs no longer use thunks 2013-09-10 16:15:41 -07:00
Henry Cook
ee98cd8378 new enum syntax 2013-09-10 10:54:51 -07:00
Stephen Twigg
e23e8e3850 Merge branch 'master' into chisel-v2 
Conflicts:
	src/main/scala/memserdes.scala
 2013-09-05 16:17:34 -07:00
Yunsup Lee
b01fe4f6aa fix memserdes bit ordering 2013-08-24 15:24:17 -07:00
Henry Cook
9aff60f340 whitespace error in build.sbt 2013-08-21 16:16:42 -07:00
Henry Cook
dc53529156 added resolver, bumped chisel dependency 2013-08-21 16:00:51 -07:00
Henry Cook
b80f45f8f2 Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2 
Conflicts:
	src/main/scala/llc.scala
	src/main/scala/slowio.scala
 2013-08-15 16:22:12 -07:00
Henry Cook
3763cd0004 standardizing sbt build conventions 2013-08-15 15:57:16 -07:00
Henry Cook
17d404b325 final Reg changes 2013-08-15 15:27:38 -07:00
Henry Cook
1308c08baa Reg standardization 2013-08-13 17:52:53 -07:00
Henry Cook
7ff4126d04 Abstracted UncachedTileLinkIOArbiters 2013-08-13 00:01:11 -07:00
Henry Cook
9162fbc9b5 Clean up cloning in tilelink bundles 2013-08-12 23:15:54 -07:00
Huy Vo
d5c9eb0f54 reset -> resetVal, getReset -> reset 2013-08-12 20:52:18 -07:00
Henry Cook
5c7a1f5cd6 initial attempt at upgrade 2013-08-12 10:36:44 -07:00
Henry Cook
bc2b45da12 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 14:55:06 -07:00
Henry Cook
d8440b042a Make compatible with scala 2.10. Refactor constants into package object. Remove networking primitives from package object. Clean up request generators. Chnage ++ to +: for appending to io.incoherent. 2013-07-24 23:22:36 -07:00
Henry Cook
db8e5fda9b new tilelink arbiter types, reduced release xact trackers 2013-07-09 15:37:42 -07:00
Henry Cook
9631b6081e Merge branch 'tilelink-data' 
Conflicts:
	src/package.scala
 2013-05-23 14:53:10 -07:00
Henry Cook
cf02f1ef01 use new locking round robin arbiter 2013-05-23 14:16:50 -07:00
Henry Cook
4c1f105ce9 added PairedData link type with matching crossbar, ported tilelink and uncore to use 2013-05-21 17:19:07 -07:00
Andrew Waterman
0672773c1a for now, don't use asserts outside of components 2013-05-09 02:14:44 -07:00
Henry Cook
9a3b2e7006 new paired meta/data IO type, and matching arbiter 2013-05-01 17:18:12 -07:00
Henry Cook
9a258e7fb4 use new locking round robin arbiter 2013-04-30 17:10:06 -07:00
Henry Cook
fedc2753e4 make sure master_xact_id field is large enough for temporary extra release trackers 2013-04-30 11:03:34 -07:00
Henry Cook
12d394811e Allow release data to be written out even before all releases have been collected 2013-04-29 18:48:31 -07:00
Henry Cook
766d5622b1 Prevent messages from becoming interleaved in the BasicCrossbar. Remove dependency trackers from the uncore, use msg headers instead. Have one ReleaseHnadler per core for now. 2013-04-10 13:46:31 -07:00
Henry Cook
74187c2068 Always route voluntary releases to ReleaseTracker to ensure all grants are sent 2013-04-09 14:09:55 -07:00
Andrew Waterman
7ff5b5b86f treat load-reserved as a non-dirtying store 2013-04-07 19:25:26 -07:00
Andrew Waterman
3479f1c6cd add LR/SC support 2013-04-07 19:25:20 -07:00
Henry Cook
b6cc08e8ca override io in LogicalNetwork 2013-03-28 14:09:48 -07:00
Henry Cook
67fc09f62e Fixes after merge, and always self probe. 2013-03-25 19:12:19 -07:00
Henry Cook
06f5de3b68 Merge branch 'release-xacts' 
Conflicts:
	src/package.scala
	src/uncore.scala
 2013-03-20 17:38:46 -07:00
Henry Cook
4d007d5c40 changed val names in hub to match new tilelink names 2013-03-20 17:14:07 -07:00
Henry Cook
c36b1dfa30 Cleaned up uncore and coherence interface. Removed defunct broadcast hub. Trait-ified tilelink bundle components. Added generalized mem arbiter. 2013-03-20 15:52:39 -07:00
Henry Cook
319b4544d7 nTiles -> nClients in LogicalNetworkConfig 2013-03-20 14:30:16 -07:00
Henry Cook
a7ae7e5758 Cleaned up self-probes 2013-03-20 14:28:20 -07:00
Andrew Waterman
7b019cb0da rmeove aborts 2013-03-19 15:30:23 -07:00
Yunsup Lee
f120800aa2 add DRAMSideLLCNull 2013-03-19 00:41:28 -07:00
Yunsup Lee
717a78f964 fix seqRead inference 2013-03-19 00:41:09 -07:00
Henry Cook
9f0ccbeac5 writebacks on release network pass asm tests and bmarks 2013-02-28 18:13:41 -08:00
Andrew Waterman
944f56a766 remove duplicate definitions 2013-02-28 14:55:19 -08:00
Henry Cook
47a632cc59 added support for voluntary wbs over the release network 2013-01-28 16:39:45 -08:00
Henry Cook
1134bbf1a4 cleanup disconnected io pins (overwritten network headers) 2013-01-27 11:59:17 -08:00
Andrew Waterman
1945fa898b make external clock divider programmable 2013-01-24 23:40:47 -08:00
Henry Cook
b5ccdab514 changed val names in hub to match new tilelink names 2013-01-22 20:09:21 -08:00
Henry Cook
c211d74e95 New TileLink names 2013-01-21 17:17:26 -08:00
Henry Cook
fb2644760f single-ported coherence master 2013-01-16 23:57:35 -08:00
Henry Cook
f7c0152409 Refactored packet headers/payloads 2013-01-15 15:52:47 -08:00
Henry Cook
418e3fdf50 Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink 2013-01-07 13:57:48 -08:00
Henry Cook
400d48e3de Refactored uncore conf 2012-12-13 11:39:14 -08:00
Henry Cook
6d61baa6cd Initial version of phys/log network compiles 2012-12-12 11:08:50 -08:00
Henry Cook
f359518e52 wip: new network classes 2012-12-12 11:08:50 -08:00
Andrew Waterman
aae7a67781 fix llc refill/writeback bugs 2012-12-06 02:07:03 -08:00
Andrew Waterman
50e9d952e8 don't initiate llc refill until writeback drains 2012-12-04 06:57:53 -08:00
Andrew Waterman
8103676b37 reduce physical address space to 4GB 2012-11-26 20:54:56 -08:00
Andrew Waterman
56f9b9721d treat prefetches as read requests 2012-11-20 05:38:49 -08:00
Yunsup Lee
6bd4f93f8c pull out prefetch commands from isRead 2012-11-18 03:13:17 -08:00
Andrew Waterman
3e6dc35809 issue self-probes for uncached read transactions 
this facilitates I$ coherence.  but it seems like a hack and perhaps
the mechanism should be rethought.
 2012-11-16 02:37:56 -08:00
Henry Cook
0cd0f8a9db Initial version of migratory protocol 2012-10-23 18:01:53 -07:00
Andrew Waterman
2aecb0024f UncoreConfiguration now contains coherence policy 2012-10-18 16:57:28 -07:00
Andrew Waterman
ffda0e41a9 parameterize width of MemSerdes/MemDesser 2012-10-18 16:56:36 -07:00
Henry Cook
9df5cfa552 Factored out tilelink classes 2012-10-16 14:26:33 -07:00
Henry Cook
8509cda813 Refined traits for use with rocket asserts, added UncoreConfiguration to handle ntiles 2012-10-16 13:58:18 -07:00
Henry Cook
1418604bf0 new constants organization 2012-10-15 18:52:48 -07:00
Huy Vo
08ab076217 forgot to change package + using fromBits in memserdes instead of manual unpacking 2012-10-10 15:42:39 -07:00
Huy Vo
9610622ab0 moving memserdes + slowio into src 2012-10-10 12:41:11 -07:00
Huy Vo
35f213e735 Merge branch 'master' of ../rocket-clone 2012-10-10 12:39:48 -07:00
Andrew Waterman
3973aef938 handle structural hazard on LLC tags 2012-10-09 18:04:55 -07:00
Huy Vo
916c1019af fixed memdessert unpacking 2012-10-09 13:03:17 -07:00
Huy Vo
cf8f20584e factoring out uncore into separate uncore repo 2012-10-01 16:08:41 -07:00
Huy Vo
2413763f3d henry's uncore and rocket changes for new xact types 2012-10-01 16:05:37 -07:00
Henry Cook
da6ec486f1 uncore and rocket changes for new xact types 2012-10-01 10:47:36 -07:00
Huy Vo
fa8075570a move srcs into src dir, factoring out uncore consts into consts 2012-09-27 12:59:45 -07:00
Andrew Waterman
6546dc84e2 rename queue to Queue 
fixes build with case-insensitive file system
 2012-08-08 22:11:59 -07:00
Andrew Waterman
aa7fd1f40b rename queue to Queue 
fixes build with case-insensitive file system
 2012-08-08 22:11:59 -07:00
Andrew Waterman
17dc2075dd fix some LLC control bugs 2012-08-06 17:10:04 -07:00
Andrew Waterman
115c25c34b fix some LLC control bugs 2012-08-06 17:10:04 -07:00
Andrew Waterman
875f3622af fix deadlock in coherence hub 2012-08-03 19:00:03 -07:00
Andrew Waterman
962423d2d1 fix deadlock in coherence hub 2012-08-03 19:00:03 -07:00
Andrew Waterman
e346f21725 fix control bug in LLC 
structural hazard on tag ram caused deadlock
 2012-08-03 18:59:37 -07:00
Andrew Waterman
92b7504c9a fix control bug in LLC 
structural hazard on tag ram caused deadlock
 2012-08-03 18:59:37 -07:00
Andrew Waterman
7a75334bb9 pipeline LLC further 2012-07-31 17:45:14 -07:00
Andrew Waterman
7b9cfd0b90 pipeline LLC further 2012-07-31 17:45:14 -07:00
Andrew Waterman
8db233c9b7 further pipeline the LLC 2012-07-30 20:12:11 -07:00
Andrew Waterman
85dc34df80 further pipeline the LLC 2012-07-30 20:12:11 -07:00
Yunsup Lee
4d4e28c138 remove reset pin on llc 2012-07-28 21:14:51 -07:00
Yunsup Lee
914b6b622d remove reset pin on llc 2012-07-28 21:14:51 -07:00
Yunsup Lee
465f2efca7 add reset pin to llc 2012-07-27 18:44:39 -07:00
Yunsup Lee
0a2d284d24 add reset pin to llc 2012-07-27 18:44:39 -07:00
Andrew Waterman
1ae3091261 memory system bug fixes 2012-07-26 00:05:21 -07:00
Andrew Waterman
1405718ca8 memory system bug fixes 2012-07-26 00:05:21 -07:00
Yunsup Lee
7736405726 fix bug in coherence hub, respect xact_rep.ready 2012-07-23 20:56:55 -07:00
Yunsup Lee
d0e12c13f6 fix bug in coherence hub, respect xact_rep.ready 2012-07-23 20:56:55 -07:00
Andrew Waterman
df8aff0906 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Andrew Waterman
c6ac836581 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Andrew Waterman
d01e70c672 decouple all interfaces between tile and top 
also, add an "incoherent" bit to tilelink to indicate no probes needed
 2012-07-17 22:55:40 -07:00
Andrew Waterman
0258dfb23f decouple all interfaces between tile and top 
also, add an "incoherent" bit to tilelink to indicate no probes needed
 2012-07-17 22:55:40 -07:00
Huy Vo
a79747a062 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Huy Vo
18bc14058b INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Andrew Waterman
62a3ea4113 fix some LLC bugs 2012-07-11 17:56:39 -07:00
Andrew Waterman
0aa33bf909 fix some LLC bugs 2012-07-11 17:56:39 -07:00
Andrew Waterman
1ebfeeca8a add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
 2012-07-10 05:23:29 -07:00
Andrew Waterman
66cf690261 add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
 2012-07-10 05:23:29 -07:00
Huy Vo
166b857055 ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
Huy Vo
0c6bade592 ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
Huy Vo
9b3161920f moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Huy Vo
f2942f79f9 moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Huy Vo
6f2f1ba21c removing wires 2012-05-24 10:42:39 -07:00
Huy Vo
0208e9f95e removing wires 2012-05-24 10:42:39 -07:00
Andrew Waterman
f804c57bb0 reduce HTIF clock divider for now 2012-05-03 04:21:11 -07:00
Henry Cook
99bc99f2ad Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle 2012-04-24 17:17:42 -07:00
Henry Cook
00155f4bc4 Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle 2012-04-24 17:17:42 -07:00
Henry Cook
d61e6ee080 Fixed coherence bug: probe counting for single tile 2012-04-24 17:17:13 -07:00
Henry Cook
37eb1a4ae6 Fixed coherence bug: probe counting for single tile 2012-04-24 17:17:13 -07:00
Henry Cook
4a6c7dbc26 Policy determined by constants. MSI policy added. 2012-04-11 17:56:59 -07:00
Andrew Waterman
98a5d682a5 coherence mostly works now 2012-04-10 02:22:45 -07:00
Andrew Waterman
2a7d2888a7 coherence mostly works now 2012-04-10 02:22:45 -07:00
Henry Cook
1920c97066 Refactored coherence as member rather than trait. MI and MEI protocols. 2012-04-10 00:09:58 -07:00
Henry Cook
b22d7f8192 Refactored coherence as member rather than trait. MI and MEI protocols. 2012-04-10 00:09:58 -07:00
Henry Cook
5acf1d9820 defined abstract coherence traits in base trait, added Incoherent trait, cleaned up incoherent policy 2012-04-09 23:29:32 -07:00
Henry Cook
e71e3ce38f defined abstract coherence traits in base trait, added Incoherent trait, cleaned up incoherent policy 2012-04-09 23:29:32 -07:00
Henry Cook
a68f5e016d changed coherence type width names to represent max sizes for all protocols 2012-04-09 23:29:32 -07:00
Henry Cook
17a5d26c1e changed coherence type width names to represent max sizes for all protocols 2012-04-09 23:29:32 -07:00
Henry Cook
f7307ee411 changed coherence message type names 2012-04-09 23:29:31 -07:00
Henry Cook
6bc47a55b4 changed coherence message type names 2012-04-09 23:29:31 -07:00
Henry Cook
d301336c33 Refactored coherence better from uncore hub, better coherence function names 2012-04-09 23:29:31 -07:00
Henry Cook
27e3346c14 Refactored coherence better from uncore hub, better coherence function names 2012-04-09 23:29:31 -07:00
Andrew Waterman
73d8d42515 fix coherence bug with multiple probe replies 2012-04-09 21:40:35 -07:00
Andrew Waterman
257747a3a1 no dessert tonight :( 2012-03-26 23:50:09 -07:00
Andrew Waterman
25fe46dc18 remove bug from dessert 2012-03-26 14:18:57 -07:00
Andrew Waterman
4e6302fedc add dessert 2012-03-25 23:03:20 -07:00
Andrew Waterman
5a00143035 loop host.in to host.out during reset 2012-03-25 21:45:10 -07:00
Andrew Waterman
a7ebea13fc add mem serdes unit 2012-03-25 17:03:58 -07:00
Yunsup Lee
5f69c5a764 fix bug in coherence hub, specifically in abort handling logic 2012-03-20 02:16:28 -07:00
Andrew Waterman
e38114e4b0 fix coherence bug 
popping wrong store dependence queue
 2012-03-16 01:24:07 -07:00
Andrew Waterman
3129040bda use divided clk for htif. UDPATE YOUR FESVR 
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
 2012-03-15 18:36:51 -07:00
Andrew Waterman
77c405ffa1 use broadcast hub and coherent HTIF 2012-03-14 16:44:35 -07:00
Andrew Waterman
53cd543d3f fix minor coherence bugs 2012-03-13 19:10:54 -07:00
Andrew Waterman
53d69d3006 parameterize broadcast hub by # of tiles 2012-03-13 17:12:01 -07:00
Andrew Waterman
1258f31825 add probe unit 2012-03-13 16:43:51 -07:00
Henry Cook
23c822a82e fix hit logic for amos 2012-03-12 22:01:52 -07:00
Henry Cook
95f880da70 fixed abort bug 2012-03-12 22:01:52 -07:00
Henry Cook
cb5ce3fe73 More broadcast hub bugfixes 2012-03-11 14:17:27 -07:00
Andrew Waterman
d777f1cb24 fix null hub store ack bug 2012-03-10 15:19:12 -08:00
Henry Cook
2014db41bd Special cased NTILES == 1 due to log2up revision 2012-03-09 11:04:58 -08:00
Henry Cook
2df5c19f13 Added require_ack field to TransactionReply bundle 2012-03-08 18:07:44 -08:00
Henry Cook
ca5caf898c Hub addr comparison bug fix 2012-03-08 16:39:05 -08:00
Henry Cook
3fc94d627d Fixed dependency queue bug in Broadcast Hub 2012-03-08 11:36:10 -08:00
Andrew Waterman
df6ac34821 coherence hub fixes 2012-03-07 21:03:44 -08:00
Henry Cook
1a90e2a162 Broadcast hub bug fixes for load uncached mem req and store uncached xact rep 2012-03-07 11:40:49 -08:00
Andrew Waterman
7929600874 change D$ to use FourStateCoherence protocol 
instead of ThreeStateIncoherence.
 2012-03-07 01:26:35 -08:00
Henry Cook
35ffb80911 unified coherence trait functions 2012-03-06 17:33:11 -08:00
Henry Cook
1e02618cc8 hub code cleanup 2012-03-06 17:01:47 -08:00
Henry Cook
762f2551a7 newTransactionOnMiss() 2012-03-06 15:54:41 -08:00
Henry Cook
3874da4a4f Added store dependency queues to BroadcastHub. Minor improvements to utils. 2012-03-06 15:54:41 -08:00
Andrew Waterman
012b991ffe implement transaction finish messages 2012-03-06 15:48:08 -08:00
Andrew Waterman
1024a460f2 support memory transaction aborts 2012-03-06 00:35:02 -08:00
Henry Cook
82822dfeec Added aborted data dequeueing state machine for BroadcastHub 2012-03-05 17:44:30 -08:00
Henry Cook
a49625c114 Broadcast hub control logic bugfixes and code cleanup 2012-03-05 17:27:55 -08:00
Yunsup Lee
802f857cb6 fix store prefetch bug, it no longer occupies an entry in the sdq 2012-03-03 15:14:59 -08:00
Henry Cook
7846d5e01d Removed has_data fields from all coherence messages, increased message type names to compensate 2012-03-02 23:51:53 -08:00
Henry Cook
d76f664007 Filled out 4 state coherence functions for cache 2012-03-02 21:58:50 -08:00
Henry Cook
993341d27e Correction to probe reply w/ data handling 2012-03-02 17:20:22 -08:00
Andrew Waterman
6ad7aa5cdc flip direction of ioPipe to match ioDecoupled 2012-03-02 16:18:32 -08:00
Henry Cook
9ad4fd5814 BroadcastHub can be elaborated by C and vlsi backends 2012-03-02 12:19:27 -08:00
Yunsup Lee
bef59527d6 clean up ioDecoupled/ioPipe interface 2012-03-01 20:48:46 -08:00
Andrew Waterman
4c3f7a36ce clean up D$ store data unit 2012-03-01 19:20:00 -08:00
Henry Cook
de73eef409 Fixed elaboration errors in LockingArbiter and BoradcastHub. Fixed ioDecoupled direction error in XactTracker 2012-03-01 18:24:22 -08:00
Henry Cook
2152b0283d Made xact_rep an ioValid, removed has_data member 2012-03-01 18:24:21 -08:00
Henry Cook
4e33b68bea Unified hub ios. Fixed some hub elaboration errors. 2012-03-01 01:20:57 -08:00
Henry Cook
940027a888 Finished broadcast hub with split mem req types. Untested. 2012-02-29 17:58:15 -08:00
Andrew Waterman
8b519e7ea8 replace tile memory interface with ioTileLink 
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
 2012-02-29 03:10:47 -08:00
Henry Cook
ef94f13087 Broadcast hub nears completion. Still does not handle generation/arbitration for decoupled mem reqs. 2012-02-29 02:59:27 -08:00
Henry Cook
6304aa992f Fixed race between read resps/reps and write req/reps in null hub 2012-02-29 00:44:03 -08:00
Andrew Waterman
eec369a1c7 separate memory request command and data 
also, merge some VLSI/C++ test harness functionality
 2012-02-28 19:06:23 -08:00
Henry Cook
e15284d22c Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem 2012-02-28 17:33:32 -08:00
Henry Cook
ffc7652e01 Null coherence hub. Begin work on internal tracker logic 2012-02-27 19:10:15 -08:00
Andrew Waterman
7d331858e2 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Henry Cook
3393dc2d31 Added probe_req ready sigs, GenArray to Vec 2012-02-27 11:26:18 -08:00
Henry Cook
70cdf869ac probe req transactors in coherence hub 2012-02-27 09:24:33 -08:00
Henry Cook
b6e6d603cc xact init transactors in coherence hub 2012-02-27 09:24:32 -08:00
Huy Vo
e22106af3f updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit 2012-02-26 17:24:08 -08:00
Yunsup Lee
ca2e70454e change package name and sbt project name to rocket 2012-02-25 17:09:26 -08:00
Henry Cook
8856e2b8bb More stylish bundle param names, some hub progress 2012-02-25 15:27:53 -08:00
Henry Cook
dfdcb7c696 Better foldR 2012-02-25 15:27:09 -08:00
Henry Cook
b3cf8f3f35 Better abstraction of data bundles 2012-02-25 12:57:01 -08:00
Henry Cook
1dcf25586f finished xact_finish and xact_abort transactors in coherence hub 2012-02-23 18:12:50 -08:00
Henry Cook
ffb88467db finished xact_rep transactor in coherence hub 2012-02-23 17:50:02 -08:00
Henry Cook
c3646e2e64 Improved TileIO organization, beginnings of hub implementation 2012-02-22 18:24:52 -08:00
Henry Cook
33a26424bd Refining tilelink interface 2012-02-22 12:15:47 -08:00
Henry Cook
b9c42a80c8 Added coherence message type enums 2012-02-22 12:15:47 -08:00
Henry Cook
cfb818aa97 Abstract class for coherence policies 2012-02-16 12:59:38 -08:00
Henry Cook
ecbf47fe16 Replace nbcache manipulation of meta state bits with abstracted functions 2012-02-16 10:43:40 -08:00
Henry Cook
76cacbd991 Added coherence tile function defs, with traits and constants 2012-02-16 00:16:45 -08:00