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Author SHA1 Message Date
Henry Cook 74b6a8d02b Refactor Tile to use cake pattern (#502) 
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
 2017-01-16 18:24:08 -08:00
Wesley W. Terpstra 52bb6cd9d9 Configs: use a uniform syntax without Match exceptions (#507) 
* Configs: use a uniform syntax without Match exceptions

The old style of specifying Configs used total functions.  The only way to
indicate that a key was not matched was to throw an exception.  Not only was
this a performance concern, but it also caused confusing error messages
whenever you had a match failure from a lookup within a lookup.  The
exception could get handled by an outer-lookup that then reported the wrong
key as missing.
 2017-01-13 14:41:19 -08:00
Wesley W. Terpstra 020fbe8be9 diplomacy: make config.Parameters available in bundle connect() 
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
 2016-12-07 12:24:01 -08:00
Henry Cook f3d0692619 Make a directory for the config package (#464) 
* [config] make dir structure mirror packages

* [config] expunge max_int
 2016-12-05 10:42:16 -08:00
Henry Cook d0a0c887dc [tracegen] decrease default address bag size (#462) 
while increasing the default number of requests.
 2016-12-04 22:46:55 -08:00
Wesley W. Terpstra b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra 9f1c668c4f config: when modifying Parameters, subordinate lookups use top 2016-11-23 20:44:45 -08:00
Henry Cook dae6772624 factor out common cache subcomponents into uncore.util 2016-11-23 12:09:35 -08:00
Henry Cook c65c255815 [coreplex] TileId moved to groundtest 2016-11-23 12:08:45 -08:00
Wesley W. Terpstra 13190a5de0 rocketchip: re-add AXI4 interface 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra a140b07009 rocketchip: cut coreplex from rocketchip 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra 5fe107bb07 rocket: pass scratchpad address to block dcache 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra d1328a6b6f rocketchip: remove most uses of GlobalAddrMap 2016-11-18 19:38:02 -08:00
Wesley W. Terpstra 10dd6070ad groundtest: gracefully handle zero uncached ports 2016-11-18 17:26:28 -08:00
Wesley W. Terpstra 8059d33217 groundtest: simplify FancyMemtestConfig for now 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 04b9a68ea6 MergedPutRegression: wait for all Puts if tlMaxClientXacts != 3 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra cd19bf65b8 regression: fix bad regression that deadlocks SoC with illegal D stall 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 5f7fa3dae5 regression: remove illegal test which reuses the same ID 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra a6188efc41 rocketchip: break infinite Config loops 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 30425d1665 rocketchip: eliminate all Knobs 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra 179c93db42 tilelink2 broadcast: make it controlled via Config 2016-11-17 17:26:49 -08:00
Wesley W. Terpstra f4ca5ea1f3 rocketchip: match simulated memory width to ExtMem.beatBytes 2016-11-17 15:40:47 -08:00
Wesley W. Terpstra 8a0ecdaaad groundtest: ComparatorConfig lives again 2016-11-17 11:07:49 -08:00
Henry Cook 92e233d596 [groundtest] testramaddr constant in package 2016-11-16 18:42:56 -08:00
Henry Cook 75d4347192 [groundtest] runs tests with new coreplex and top 2016-11-16 17:05:53 -08:00
Henry Cook 408e78e35e rocketchip Periphery: ExtMem and ExtBus Configs 2016-11-16 16:50:30 -08:00
Wesley W. Terpstra 3703ed39f7 groundtest: PTW needs atomics 2016-11-16 12:16:54 -08:00
Wesley W. Terpstra 10e459fedb rocket: change connection between rocketchip and coreplex 
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
 2016-11-15 18:27:52 -08:00
Henry Cook 2d68f12115 [tl2] give groundtest tile some output nodes 2016-11-14 18:09:40 -08:00
Henry Cook 71315d5cf5 WIP scala compile and firrtl elaborate; monitor error 2016-11-11 13:07:45 -08:00
Henry Cook afa1a6d549 WIP uncore and rocket changes compile 2016-11-10 15:57:29 -08:00
Wesley W. Terpstra 32fd11935c rocketchip: use TL2 and AXI4 for memory subsytem 2016-11-04 13:36:47 -07:00
Wesley W. Terpstra aabd17d935 rocketchip: must create bundles within Module scope 
1. Bundles be created after base class Module constructor runs
2. Bundles must be created before Module(...) runs

Solution: pass a bundle constructor to the cake base class

Require the constructor to take a parameter so people don't use it by
accident; they should get a type error.

Consistently name all the cake arguments with an _io, _coreplex, _outer,
so that they don't shadow the base class variables you should be using.
 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra ac886026e6 rocketchip: reduce number of type parameters 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 015c3b862a diplomacy: print out bus widths on edges in agent graph 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 0cc00e7616 regressions: test scratchpad 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra 545154c1c3 groundtest: make it happy with TL2 addressing 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra e9725aea2f rocketchip: all of the address map now comes from TL2 2016-10-31 11:42:44 -07:00
Wesley W. Terpstra a73aa351ca rocketchip: fix all clock crossings 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra 825c253a72 rocketchip: move TL2 and cake pattern into Coreplex 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra dddb50a942 BuildTiles: convert to LazyTile 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra c3dacca39a rocketchip: remove pbus; TL2 has swallowed it completely 2016-10-31 11:42:08 -07:00
Wesley W. Terpstra 0ae45d0f24 rocketchip: bundle (=> B) need not be delayed; Module is constructed later 2016-10-31 11:41:18 -07:00
Howard Mao cb81ea516c add regression test for put-after-release bug 2016-10-28 18:26:34 -07:00
Howard Mao fa8844d5c3 properly use rocket MT_ constants in regression tests 2016-10-28 18:26:34 -07:00
Wesley W. Terpstra f05298d9bc tilelink2: move general-purpose code out of tilelink2 package 2016-10-03 16:22:28 -07:00
Howard Mao 9910c69c67 Move a bunch more things into util package 
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util
 2016-09-29 14:23:42 -07:00
Howard Mao c45cc76cef Get rid of remaining MemIO code 
The only thing we were still using it for was for the MIFDataBits
and MIFTagBits parameters. We replace these with EdgeDataBits and
EdgeIDBits.
 2016-09-27 16:28:17 -07:00
Howard Mao 18e7ea89f2 Get rid of broken groundtests 
The NastiConverterTest, PCIeMockupTest, and DirectGroundtest
configurations have been broken by recent changes.

The NastiConverterTest has been superseded by a unit test and the
other two were only created for an attempt at FPGA debugging.
They weren't actually very useful for that purpose, so might as well get
rid of them.
 2016-09-27 16:28:17 -07:00
Howard Mao 71a9c78e4b add WidthAdapter from AXI slave to Coreplex TL slave 2016-09-27 12:48:01 -07:00
Howard Mao 7d6fb950b6 Give TileLink IDs more sensible names 
* Outermost -> MCtoEdge
 * MMIO_Outermost -> MMIOtoEdge

Then the corresponding parameters objects are

 * L1toL2 -> innerParams
 * L2toMC -> outerMemParams
 * L2toMMIO -> outerMMIOParams
 * MCtoEdge -> edgeMemParams
 * MMIOtoEdge -> edgeMMIOParams
 2016-09-27 12:48:01 -07:00
Howard Mao c741ada619 get TraceGen working again 2016-09-26 17:28:21 -07:00
Henry Cook 673efb400d Merge branch 'master' into unittest-config 2016-09-22 16:20:53 -07:00
Henry Cook 1e54820f8c Merge remote-tracking branch 'origin/master' into unittest-config 2016-09-22 16:03:51 -07:00
Henry Cook 411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. 2016-09-22 15:59:29 -07:00
Wesley W. Terpstra 9f1f6fc61f Comparator: tolerate mismatched data when it is undefined 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra 0a3718881f rocketchip: re-enable testing of atomics 2016-09-22 15:18:54 -07:00
Henry Cook 83c08a931d [WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator 2016-09-22 14:57:18 -07:00
Henry Cook 47c5d1a992 [WIP] Move RocketTestSuite generation into RocketchipGenerator 2016-09-22 14:31:45 -07:00
Yunsup Lee 5bb575ef74 rename internal/external MMIO network to cbus/pbus respectively 2016-09-21 18:29:28 -07:00
Yunsup Lee 7afd630d3e add multiclock support to Coreplex 2016-09-21 16:55:26 -07:00
Henry Cook 335e866176 [unittest] Parallelize UnitTestSuite (#319) 
* [unittest] Parallelize UnitTestSuite so all tests have their own timer, runs until all finish or any timeout. Adds SimpleTimer.

* [util] Timer spacing cleanup

* [unittest] Remove Config reference to UnitTestTimeout
 2016-09-21 13:05:22 -07:00
Richard Xia 3fdf40c088 Change implicit argument to explicit. 2016-09-16 17:47:31 -07:00
Richard Xia 63f13ae7ce Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor 2016-09-16 17:10:52 -07:00
Wesley W. Terpstra 38a9421c75 Comparator: don't compare addr_beat when it's irrelevant 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 669e3b0d96 Regression: fix-up address lookup 2016-09-15 21:28:56 -07:00
Henry Cook be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs 2016-09-15 13:04:01 -07:00
Yunsup Lee 710f1ec020 Move BootROM from Coreplex to Periphery 2016-09-14 16:09:59 -07:00
Howard Mao 1882241493 move junctions utils into top-level utils package 2016-09-13 20:47:04 -07:00
Henry Cook 7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. 2016-09-13 20:30:14 -07:00
Yunsup Lee bb3f514e8d now able to add periphery devices through traits 
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
 2016-09-10 23:39:29 -07:00
Andrew Waterman c05ba1e864 Add TileId parameter, generalizing GroundTestId 
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
 2016-09-02 00:10:50 -07:00
Howard Mao 50d6738caf make sure DummyPTW sets all the necessary status and ptbr signals 2016-08-31 22:00:27 -07:00
Howard Mao 7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00