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125 Commits

Author SHA1 Message Date
Howard Mao 71a9c78e4b add WidthAdapter from AXI slave to Coreplex TL slave 2016-09-27 12:48:01 -07:00
Howard Mao 7d6fb950b6 Give TileLink IDs more sensible names 
* Outermost -> MCtoEdge
 * MMIO_Outermost -> MMIOtoEdge

Then the corresponding parameters objects are

 * L1toL2 -> innerParams
 * L2toMC -> outerMemParams
 * L2toMMIO -> outerMMIOParams
 * MCtoEdge -> edgeMemParams
 * MMIOtoEdge -> edgeMMIOParams
 2016-09-27 12:48:01 -07:00
Howard Mao c741ada619 get TraceGen working again 2016-09-26 17:28:21 -07:00
Henry Cook 673efb400d Merge branch 'master' into unittest-config 2016-09-22 16:20:53 -07:00
Henry Cook 1e54820f8c Merge remote-tracking branch 'origin/master' into unittest-config 2016-09-22 16:03:51 -07:00
Henry Cook 411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. 2016-09-22 15:59:29 -07:00
Wesley W. Terpstra 9f1f6fc61f Comparator: tolerate mismatched data when it is undefined 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra 0a3718881f rocketchip: re-enable testing of atomics 2016-09-22 15:18:54 -07:00
Henry Cook 83c08a931d [WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator 2016-09-22 14:57:18 -07:00
Henry Cook 47c5d1a992 [WIP] Move RocketTestSuite generation into RocketchipGenerator 2016-09-22 14:31:45 -07:00
Yunsup Lee 5bb575ef74 rename internal/external MMIO network to cbus/pbus respectively 2016-09-21 18:29:28 -07:00
Yunsup Lee 7afd630d3e add multiclock support to Coreplex 2016-09-21 16:55:26 -07:00
Henry Cook 335e866176 [unittest] Parallelize UnitTestSuite (#319) 
* [unittest] Parallelize UnitTestSuite so all tests have their own timer, runs until all finish or any timeout. Adds SimpleTimer.

* [util] Timer spacing cleanup

* [unittest] Remove Config reference to UnitTestTimeout
 2016-09-21 13:05:22 -07:00
Richard Xia 3fdf40c088 Change implicit argument to explicit. 2016-09-16 17:47:31 -07:00
Richard Xia 63f13ae7ce Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor 2016-09-16 17:10:52 -07:00
Wesley W. Terpstra 38a9421c75 Comparator: don't compare addr_beat when it's irrelevant 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra 669e3b0d96 Regression: fix-up address lookup 2016-09-15 21:28:56 -07:00
Henry Cook be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs 2016-09-15 13:04:01 -07:00
Yunsup Lee 710f1ec020 Move BootROM from Coreplex to Periphery 2016-09-14 16:09:59 -07:00
Howard Mao 1882241493 move junctions utils into top-level utils package 2016-09-13 20:47:04 -07:00
Henry Cook 7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. 2016-09-13 20:30:14 -07:00
Yunsup Lee bb3f514e8d now able to add periphery devices through traits 
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
 2016-09-10 23:39:29 -07:00
Andrew Waterman c05ba1e864 Add TileId parameter, generalizing GroundTestId 
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
 2016-09-02 00:10:50 -07:00
Howard Mao 50d6738caf make sure DummyPTW sets all the necessary status and ptbr signals 2016-08-31 22:00:27 -07:00
Howard Mao 7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00