Get rid of broken groundtests
The NastiConverterTest, PCIeMockupTest, and DirectGroundtest configurations have been broken by recent changes. The NastiConverterTest has been superseded by a unit test and the other two were only created for an attempt at FPGA debugging. They weren't actually very useful for that purpose, so might as well get rid of them.
This commit is contained in:
Howard Mao
parent
c77c244016
commit
18e7ea89f2
@ -50,12 +50,6 @@ class BufferlessRegressionTestConfig extends Config(
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class CacheRegressionTestConfig extends Config(
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new WithCacheRegressionTest ++ new WithL2Cache ++ new GroundTestConfig)
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class NastiConverterTestConfig extends Config(new WithNastiConverterTest ++ new GroundTestConfig)
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class FancyNastiConverterTestConfig extends Config(
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new WithNCores(2) ++ new WithNastiConverterTest ++
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new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
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new WithL2Cache ++ new GroundTestConfig)
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class TraceGenConfig extends Config(
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new WithNCores(2) ++ new WithTraceGen ++ new GroundTestConfig)
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class TraceGenBufferlessConfig extends Config(
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@ -74,9 +68,6 @@ class MIF32BitComparatorConfig extends Config(
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class MIF32BitMemtestConfig extends Config(
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new WithMIFDataBits(32) ++ new MemtestConfig)
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class PCIeMockupTestConfig extends Config(
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new WithPCIeMockupTest ++ new GroundTestConfig)
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/* Composable Configs to set individual parameters */
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class WithGroundTest extends Config(
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(pname, site, here) => pname match {
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@ -212,19 +203,6 @@ class WithCacheRegressionTest extends Config(
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case _ => throw new CDEMatchError
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})
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class WithNastiConverterTest extends Config(
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(pname, site, here) => pname match {
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case GroundTestKey => Seq.fill(site(NTiles)) {
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GroundTestTileSettings(uncached = 1)
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}
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case GeneratorKey => TrafficGeneratorParameters(
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maxRequests = 128,
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startAddress = site(GlobalAddrMap)("mem").start)
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case BuildGroundTest =>
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(p: Parameters) => Module(new NastiConverterTest()(p))
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case _ => throw new CDEMatchError
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})
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class WithTraceGen extends Config(
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topDefinitions = (pname, site, here) => pname match {
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case GroundTestKey => Seq.fill(site(NTiles)) {
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@ -252,53 +230,3 @@ class WithTraceGen extends Config(
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case "L1D_WAYS" => 1
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case _ => throw new CDEMatchError
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})
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class WithPCIeMockupTest extends Config(
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(pname, site, here) => pname match {
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case NTiles => 2
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case GroundTestKey => Seq(
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GroundTestTileSettings(1, 1),
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GroundTestTileSettings(1))
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case GeneratorKey => TrafficGeneratorParameters(
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maxRequests = 128,
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startAddress = site(GlobalAddrMap)("mem").start)
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case BuildGroundTest =>
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(p: Parameters) => p(TileId) match {
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case 0 => Module(new GeneratorTest()(p))
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case 1 => Module(new NastiConverterTest()(p))
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}
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case _ => throw new CDEMatchError
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})
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class WithDirectMemtest extends Config(
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(pname, site, here) => {
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val nGens = 8
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pname match {
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case GroundTestKey => Seq(GroundTestTileSettings(uncached = nGens))
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case GeneratorKey => TrafficGeneratorParameters(
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maxRequests = 1024,
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startAddress = 0)
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case BuildGroundTest =>
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(p: Parameters) => Module(new GeneratorTest()(p))
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case _ => throw new CDEMatchError
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}
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})
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class WithDirectComparator extends Config(
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(pname, site, here) => pname match {
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case GroundTestKey => Seq.fill(site(NTiles)) {
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GroundTestTileSettings(uncached = site(ComparatorKey).targets.size)
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}
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case BuildGroundTest =>
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(p: Parameters) => Module(new ComparatorCore()(p))
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case ComparatorKey => ComparatorParameters(
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targets = Seq(0L, 0x100L),
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width = 8,
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operations = 1000,
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atomics = site(UseAtomics),
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prefetches = site("COMPARATOR_PREFETCHES"))
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case FPUConfig => None
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case UseAtomics => false
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case "COMPARATOR_PREFETCHES" => false
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case _ => throw new CDEMatchError
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})
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@ -1,123 +0,0 @@
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package groundtest
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import Chisel._
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import uncore.tilelink._
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import uncore.converters._
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import junctions._
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import util.Timer
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import rocket.TileId
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import cde.Parameters
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class NastiGenerator(id: Int)(implicit val p: Parameters) extends Module
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with HasNastiParameters
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with HasMIFParameters
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with HasAddrMapParameters
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with HasTrafficGeneratorParameters {
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val io = new Bundle {
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val status = new GroundTestStatus
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val mem = new NastiIO
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}
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val mifDataBytes = mifDataBits / 8
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val (s_start :: s_write_addr :: s_write_data ::
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s_read :: s_wait :: s_finish :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_start)
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def ref_data(idx: UInt) = UInt(0x35abffcd, genWordBits) + (idx << UInt(3))
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val part_of_addr =
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if (log2Ceil(nGens) > 0) {
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Cat(UInt(id, log2Ceil(nGens)),
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UInt(0, wordOffset))
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} else {
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UInt(0, wordOffset)
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}
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val (write_idx, write_done) = Counter(io.mem.w.fire(), maxRequests)
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val write_addr = UInt(startAddress) + Cat(write_idx, part_of_addr)
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val write_data = Fill(mifDataBits / genWordBits, ref_data(write_idx))
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val write_align = write_addr(log2Up(mifDataBytes) - 1, 0)
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val write_mask = UInt((1 << genWordBytes) - 1, nastiWStrobeBits) << write_align
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val (read_idx, read_done) = Counter(io.mem.ar.fire(), maxRequests)
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val read_addr = UInt(startAddress) + Cat(read_idx, part_of_addr)
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io.mem.aw.valid := (state === s_write_addr)
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io.mem.aw.bits := NastiWriteAddressChannel(
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id = write_idx(nastiXIdBits - 1, 0),
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addr = write_addr,
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len = UInt(0),
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size = UInt(log2Ceil(genWordBytes)))
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io.mem.w.valid := (state === s_write_data)
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io.mem.w.bits := NastiWriteDataChannel(
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data = write_data,
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strb = Some(write_mask),
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last = Bool(true))
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io.mem.ar.valid := (state === s_read)
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io.mem.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = read_addr,
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len = UInt(0),
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size = UInt(log2Ceil(genWordBytes)))
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io.mem.r.ready := Bool(true)
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io.mem.b.ready := Bool(true)
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io.status.finished := (state === s_finish)
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val (read_resp_idx, read_resp_done) = Counter(io.mem.r.fire(), maxRequests)
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val read_resp_addr = UInt(startAddress) + Cat(read_resp_idx, part_of_addr)
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val read_offset = read_resp_addr(log2Up(nastiXDataBits / 8) - 1, 0)
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val read_shift = Cat(read_offset, UInt(0, 3))
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val read_data = (io.mem.r.bits.data >> read_shift)(genWordBits - 1, 0)
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val data_mismatch = io.mem.r.valid && read_data =/= ref_data(read_resp_idx)
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assert(!data_mismatch, "NASTI Test: results do not match")
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io.status.error.valid := data_mismatch
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io.status.error.bits := UInt(1)
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when (state === s_start) { state := s_write_addr }
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when (io.mem.aw.fire()) { state := s_write_data }
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when (io.mem.w.fire()) { state := s_write_addr }
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when (write_done) { state := s_read }
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when (read_done) { state := s_wait }
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when (read_resp_done) { state := s_finish }
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val r_timer = Module(new Timer(1000, 2))
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r_timer.io.start.valid := io.mem.ar.fire()
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r_timer.io.start.bits := io.mem.ar.bits.id
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r_timer.io.stop.valid := io.mem.r.fire() && io.mem.r.bits.last
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r_timer.io.stop.bits := io.mem.r.bits.id
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assert(!r_timer.io.timeout.valid, "NASTI Read timed out")
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val w_timer = Module(new Timer(1000, 2))
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w_timer.io.start.valid := io.mem.aw.fire()
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w_timer.io.start.bits := io.mem.aw.bits.id
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w_timer.io.stop.valid := io.mem.b.fire()
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w_timer.io.stop.bits := io.mem.b.bits.id
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assert(!w_timer.io.timeout.valid, "NASTI Write timed out")
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io.status.timeout.valid := r_timer.io.timeout.valid || w_timer.io.timeout.valid
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io.status.timeout.bits := Mux(r_timer.io.timeout.valid, UInt(1), UInt(2))
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}
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class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p)
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with HasNastiParameters {
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require(tileSettings.uncached == 1 && tileSettings.cached == 0)
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val genId = p(GroundTestKey).take(p(TileId))
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.map(settings => settings.cached + settings.uncached)
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.foldLeft(0)(_ + _)
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val test = Module(new NastiGenerator(genId))
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val converter = Module(new TileLinkIONastiIOConverter()(
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p.alterPartial { case TLId => "EdgetoSlave" }))
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converter.io.nasti <> test.io.mem
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TileLinkWidthAdapter(io.mem.head, converter.io.tl)
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io.status := test.io.status
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}
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