Andrew Waterman
5164f947c0
Validate mstatus.mpp/dcsr.prv values on MRET/DRET
...
The registers can still hold invalid values, but an attempt to switch
to the mode stored therein will instead go to an implemented mode.
2016-08-17 15:39:34 -07:00
Andrew Waterman
ed827678ac
Write test harness in Chisel
...
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
Andrew Waterman
2d1d7266f5
Fix RV64 badaddr value on instruction faults with large addresses
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We were relying on ALU passthrough for this, but failed to override the
ALU dw argument, so bits above 31 could be discarded.
2016-08-15 23:09:09 -07:00
Howard Mao
38e0967816
strip DMA and RoCC CSRs out of rocket and uncore ( #201 )
2016-08-15 23:08:55 -07:00
Howard Mao
2645f74af2
clean up addrmap flatten function
2016-08-09 22:14:32 -07:00
Andrew Waterman
1b8f919db2
Remove unused CoreName parameter
2016-08-09 15:24:59 -07:00
Andrew Waterman
458520c8f6
Use a generic UInt for TileLink op sizes, rather than MT_xx enum
2016-08-09 15:24:51 -07:00
Andrew Waterman
a857b08c59
[rocket] compute D$ tag bits based upon # of arbiter ports
2016-08-09 14:40:48 -07:00
Howard Mao
9c4e57aea5
example Rocc accelerator fixes
2016-08-04 11:17:13 -07:00
Andrew Waterman
cc0f8962fb
[rocket] take physical memory attribute check off critical path
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Cache the attributes in the TLB instead.
2016-08-02 17:21:03 -07:00
Andrew Waterman
76f33d88a6
[rocket] Respect physical memory protection during page table walks
2016-08-02 17:20:49 -07:00
Andrew Waterman
5d4f6383f2
[rocket] Automatically kill D$ access on address exceptions
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Doing this internally to the cache eliminates a long control path
from the cache to the core and back to the cache.
2016-08-02 17:20:49 -07:00
Andrew Waterman
b54db0ba23
[rocket] don't update BTB on not-taken branches
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Only update the BHT; don't set the target prediction to pc+4.
2016-08-02 17:20:49 -07:00
Andrew Waterman
64bde1060c
[rocket] remove unused code in ibuf
2016-08-02 15:26:09 -07:00
Andrew Waterman
2ce702dc0a
[rocket] fix PTW critical path
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Pipeline the killing of a D$ request following a PTW cache hit.
2016-08-02 15:19:48 -07:00
Andrew Waterman
7e9d139e49
[rocket] remove rocket-specific require() from HasCoreParameters
2016-08-02 15:19:48 -07:00
Andrew Waterman
832e56d3c7
Fix toBits/toUInt/toSInt deprecation warnings
2016-07-31 17:13:52 -07:00
Andrew Waterman
a6e009d8de
[rocket] Fix frontend mask when fetchWidth == 1
2016-07-31 15:21:17 -07:00
Andrew Waterman
c49dad2e9d
Improve PTW QoR
2016-07-29 17:56:42 -07:00
Andrew Waterman
058396aefe
[rocket] Implement RVC
2016-07-29 17:56:42 -07:00
Andrew Waterman
c465120610
[rocket] use more standard pattern for computing integer min
2016-07-29 17:56:42 -07:00
Andrew Waterman
ffac86b041
[rocket] only write badaddr on certain exceptions
2016-07-29 17:56:42 -07:00
Andrew Waterman
0d3d9fca25
[rocket] Allow zapping of BTB entries
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This is necessary to guarantee forward progress with RVC, since if the
BTB keeps mispredicting, the processor might never successfully
fetch both halves of a misaligned instruction.
2016-07-29 17:56:42 -07:00
Andrew Waterman
8e0392f24b
[rocket] don't hard-code instruction width in BHT
2016-07-29 17:56:42 -07:00
Andrew Waterman
8a7fc75b53
fix metadata race in blocking L1 DCache
2016-07-28 17:54:28 -07:00
Howard Mao
bf35f980a6
make sure PTE cache is power of 2 in size to satisfy PseudoLRU requirement
2016-07-27 18:40:38 -07:00
Howard Mao
dcfcac9530
fix LRSC issue (RocketChip issue #86 )
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It was possible that the result of a store-conditional could get lost if it
did not depend on the result of the corresponding load-reserved.
This was because the MSHR does not update the client state based on the
secondary requests. So the LR would acquire the line in clientExcusiveClean,
but then we would fail to update the metadata array to change the state
to clientExclusiveDirty.
The solution is to track whether a secondary acquire would cause the
line to be dirty. If so, use M_XWR instead of the primary command to
generate the update coherence state.
2016-07-26 18:41:52 -07:00
Howard Mao
51edd19e85
add U bit to misa register
2016-07-22 14:22:59 -07:00
Colin Schmidt
a43ad522dc
add clock override to tile constructor ( #42 )
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useful to have upstream so that tape-outs can construct
rocket-chip to have cores on different clocks without
forking rocket
2016-07-21 17:56:52 -07:00
Ben Keller
c069e66056
Modify the RoCC interface to include status in the command queue. ( #41 )
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This addresses a bug in which changes in mstatus could
propagate to RoCCs before their time. Existing RoCCs that use
the status port will need to be modified to match this change.
This addresses the first half of #40 .
2016-07-18 17:40:50 -07:00
Howard Mao
2723b2f515
fix issues in SimpleHellaCacheIF and document the changes
2016-07-18 17:02:47 -07:00
Howard Mao
40a146f625
HellaCacheArbiter passes through if n == 1
2016-07-18 17:01:29 -07:00
mwachs5
cff8de9814
Use new Mul/Div parameters vs UseFastMulDiv ( #48 )
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* Use new Mul/Div parameters vs UseFastMulDiv
* Rename MulDivUnroll to MulUnroll
2016-07-15 15:41:20 -07:00
Andrew Waterman
7cf44f9b25
clean up WideCounter implementation
2016-07-15 00:51:01 -07:00
Andrew Waterman
d78f1aacd0
Clean up some zero-width wire cases using UInt.extract
2016-07-14 22:08:01 -07:00
Andrew Waterman
da512d4230
Explicitly discard BTB index LSBs
2016-07-14 17:10:27 -07:00
Andrew Waterman
e6aab368a4
Replace ICacheBufferWays parameter with I$ constructor argument
2016-07-14 12:38:54 -07:00
Andrew Waterman
3d0b92afd7
Misc code cleanup
2016-07-14 12:09:34 -07:00
Andrew Waterman
b8884e8143
Simplify frontend virtual address extension code
2016-07-14 12:05:09 -07:00
Andrew Waterman
1699622730
Don't speculatively refill I$ in uncacheable regions
2016-07-09 01:10:58 -07:00
Howard Mao
f7b392306e
make sure SimpleHellaCacheIF can work with blocking DCache
2016-07-07 18:59:23 -07:00
Andrew Waterman
3d8939d3c3
Set misa.base = 1 for RV32
2016-07-07 15:32:21 -07:00
Andrew Waterman
2455a806af
Make WFI instruction respect mie CSR setting
2016-07-07 15:31:17 -07:00
Andrew Waterman
35a983275e
Guarantee one-hotness of BTB entries
2016-07-06 15:58:01 -07:00
Andrew Waterman
c0e6ecebfc
Fix BTB perf bug
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In rare cases, it would replace into a different row than it recorded.
2016-07-06 03:16:05 -07:00
Andrew Waterman
f3e22984d5
Remove uarch counters
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These will be replaced with the indirect TDR scheme used by breakpoints.
2016-07-06 01:41:41 -07:00
Andrew Waterman
25fdabdd59
Don't implicitly create Vecs, since they're heavyweight
2016-07-06 01:41:31 -07:00
Andrew Waterman
8bd7e3932b
Implement priv-1.9 PTE scheme
2016-07-05 19:19:49 -07:00
Andrew Waterman
ebefe57036
simplify BTB fetchWidth=1 special case
2016-07-04 23:43:47 -07:00
Andrew Waterman
2d325df60c
Improve PTW simulation performance
2016-07-02 14:34:18 -07:00