Andrew Waterman
|
50ccc20bf3
|
replace RDNPC with AUIPC
|
2013-04-22 04:20:15 -07:00 |
|
Andrew Waterman
|
ae7720e284
|
guarantee LR/SC forward progress
the mechanism is to block new probes for several cycles after a successful LR.
this also cleans up the MSHR <-> ProbeUnit interface slightly.
|
2013-04-07 19:27:21 -07:00 |
|
Andrew Waterman
|
e74e032c87
|
simplify MSHR memory response logic
|
2013-04-06 01:03:37 -07:00 |
|
Andrew Waterman
|
1abb9277db
|
fix LR/SC atomicity violation
note, it's still not starvation-free.
|
2013-04-05 19:13:38 -07:00 |
|
Andrew Waterman
|
8cbdeb2abf
|
add LR/SC support
|
2013-04-04 17:07:09 -07:00 |
|
Andrew Waterman
|
fc46daecf6
|
don't flush pipeline on writes to side-effect-free PCRs
notably, K0, K1, and EPC
|
2013-04-04 17:07:09 -07:00 |
|
Andrew Waterman
|
8b439ef20d
|
only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
|
2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
|
d43f484feb
|
take interrupts on nonzero fromhost values
|
2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
|
d4a3351cfc
|
expose pending interrupts in status register
|
2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
|
35349d227f
|
update to new Mem style
|
2013-02-20 16:09:46 -08:00 |
|
Andrew Waterman
|
9f89c812b7
|
fix HTIF memory size reporting
|
2013-01-29 23:08:25 -08:00 |
|
Andrew Waterman
|
66eb3720a4
|
fix SRAM semantics bug in HellaFlowQueue
|
2013-01-29 21:16:42 -08:00 |
|
Andrew Waterman
|
6275e009f8
|
fix HellaQueue deq.valid signal
|
2013-01-28 20:57:43 -08:00 |
|
Andrew Waterman
|
45d8066f45
|
add HellaQueue, an SRAM-based queue
|
2013-01-28 20:54:25 -08:00 |
|
Andrew Waterman
|
37c67f1d87
|
pipeline reset to the vector unit
|
2013-01-28 17:56:32 -08:00 |
|
Andrew Waterman
|
c890099e09
|
add System Control Register space to HTIF
|
2013-01-24 23:41:24 -08:00 |
|
Andrew Waterman
|
575bd3445a
|
re-generalize scoreboard
|
2013-01-24 18:00:39 -08:00 |
|
Andrew Waterman
|
1fbc20450e
|
don't allow simultaneous reads and writes to the tag ram
|
2013-01-24 17:55:00 -08:00 |
|
Andrew Waterman
|
37ee843b2c
|
don't use reset combinationally
|
2013-01-24 17:55:00 -08:00 |
|
Andrew Waterman
|
bb6fbddf1f
|
don't probe the mshr file to inquire about refills
|
2013-01-24 17:54:59 -08:00 |
|
Andrew Waterman
|
5b9f938263
|
correctly sign-extend badvaddr, epc, and ebase
|
2013-01-24 17:54:59 -08:00 |
|
Andrew Waterman
|
667b4ee858
|
remove Queue flush port (override reset instead)
|
2012-08-22 13:39:19 -07:00 |
|
Andrew Waterman
|
d4a001b867
|
add PriorityMux; use to implement PriorityEncoder
|
2012-08-22 13:38:25 -07:00 |
|
Andrew Waterman
|
743e032f06
|
generalize interface to DecodeLogic
|
2012-08-22 13:38:07 -07:00 |
|
Andrew Waterman
|
80c243469e
|
add flow queues and skid buffers
hopefully they work
|
2012-07-30 18:47:12 -07:00 |
|
Andrew Waterman
|
2ec76390e3
|
improve PriorityEncoderOH and add Counter util
|
2012-07-30 16:06:55 -07:00 |
|
Andrew Waterman
|
7778802395
|
reduce number of outstanding transactions
|
2012-07-26 14:51:41 -07:00 |
|
Andrew Waterman
|
e496cd7584
|
use Mem to implement queues to speed things up
|
2012-07-13 21:48:05 -07:00 |
|
Andrew Waterman
|
bac82762d3
|
use only one (wide) tag ram for set assoc. caches
|
2012-07-12 14:50:12 -07:00 |
|
Andrew Waterman
|
429fcbed8e
|
fix some LLC bugs
|
2012-07-11 17:56:39 -07:00 |
|
Andrew Waterman
|
f645fb4dd7
|
add L2$
It still has performance bugs but no correctness bugs AFAIK.
|
2012-07-10 05:23:29 -07:00 |
|