df442ed82c
[rocketchip] avoid pending merge conflict]
2016-09-19 13:24:01 -07:00
ddcf1b4099
Use PROJECT rather than MODEL in name of binary and generated src files.
2016-09-19 13:23:17 -07:00
7b8aa6c839
[rocketchip] split out Base and Example tops
2016-09-19 11:00:13 -07:00
7ff7076dab
Merge pull request #310 from ucb-bar/rxia-testharness-refactor
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Resolve merge conflicts in testharness-refactor
2016-09-19 10:22:49 -07:00
f0debb89e4
Merge pull request #314 from ucb-bar/widecounter-reset
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Allow WideCounter to not be reset
2016-09-18 22:37:40 -07:00
a49814c667
Allow WideCounter to not be reset
2016-09-18 18:45:51 -07:00
aa956c0108
Merge pull request #312 from ucb-bar/tl2-cheap-address-decode
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Tl2 cheap address decode
2016-09-17 17:37:03 -07:00
9817a00ed9
tilelink2: Fuzzer should check address validity before injection
2016-09-17 17:07:21 -07:00
b11839f5a1
tilelink2: differentiate fast/safe address lookup cases
2016-09-17 17:04:18 -07:00
b4baae4214
tilelink2: minimize Xbar decode logic
2016-09-17 16:14:25 -07:00
76d8ed6a69
tilelink2: remove 'strided'; !contiguous is clearer
2016-09-17 16:14:25 -07:00
fa0f119f3c
tilelink2: consider the implications of negative address mask
2016-09-17 16:14:22 -07:00
e437508548
tilelink2: track interrupt connectivity like in TL2
2016-09-17 14:43:48 -07:00
fd3ac4653c
Merge pull request #311 from ucb-bar/rom-executable
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Rom executable
2016-09-17 01:28:52 -07:00
01c1886b9d
Utils: cacheable only if there is a cache manager
2016-09-17 00:56:21 -07:00
6c3269a1d8
SRAM: optionally (default: true) executable
2016-09-17 00:19:37 -07:00
e749558190
ROM: optionally (default: true) executable
2016-09-17 00:19:09 -07:00
c70045b8b3
Utils: express cacheability from TL2 to TL1
2016-09-17 00:16:40 -07:00
e3d2bd3323
Top: print memory region properties, RWX [C]
2016-09-17 00:16:00 -07:00
75c73fce37
Merge pull request #309 from ucb-bar/tl2-addrmap
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Tl2 addrmap
2016-09-16 19:09:22 -07:00
5c858685aa
Utils: support managers with multiple addresses
2016-09-16 18:03:49 -07:00
3fdf40c088
Change implicit argument to explicit.
2016-09-16 17:47:31 -07:00
a9382b3116
Periphery: test bench looks for "testram"
2016-09-16 17:47:20 -07:00
b5ce6150c7
Periphery: dynamically create address map + config string for TL2
2016-09-16 17:28:47 -07:00
8876d83640
Prci: preserve Andrew's preferred clint name
2016-09-16 17:28:47 -07:00
a357c1d42e
tilelink2: create DTS for devices automagically
2016-09-16 17:28:47 -07:00
2587234838
tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters
2016-09-16 17:28:47 -07:00
915a929af1
tilelink2: Nodes can now mix context into parameters
2016-09-16 17:28:47 -07:00
63f13ae7ce
Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor
2016-09-16 17:10:52 -07:00
503ce14c98
Merge pull request #307 from ucb-bar/address-shrink
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RR: undefined regs return zeros
2016-09-16 16:55:35 -07:00
dae0918c85
tilelink2 RegisterRouter: support undefZero
2016-09-16 16:09:00 -07:00
f0f553f227
tilelink2 RegisterRouterTest: work around firrtl warning
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Using io.wready leads to verilog that reads from the output...
Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
Port "io_wready" declared as output in module "RRTestCombinational_29" may
need to be inout. Coercing to inout.
2016-09-16 16:09:00 -07:00
3fcc1a4460
tilelink2 RegisterRouterTest: don't couple fire into helpers
2016-09-16 16:09:00 -07:00
2210e71f42
tilelink2 AddressDecoder: validate output of optimization
2016-09-16 16:09:00 -07:00
023a54f122
tilelink2 AddressDecoder: improved heuristic
2016-09-16 16:09:00 -07:00
4abba87b61
bump firrtl to include empty module fix for vivado ( #306 )
2016-09-16 15:53:53 -07:00
86b70c8c59
Rename PRCI to CoreplexLocalInterrupter
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That's all it's doing (there wasn't much PRC).
2016-09-16 14:26:34 -07:00
4b1de82c1d
RegField: separate UInt=>bytes and bytes=>regs
2016-09-16 14:24:28 -07:00
943c36954d
tilelink2 RegField: .bytes should update more than one byte!
2016-09-16 14:24:24 -07:00
6134384da4
Fix deprecation warnings
2016-09-16 14:24:19 -07:00
a031686763
util: Do BlackBox Async Set/Reset Registers more properly ( #305 )
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* util: Do Set/Reset Async Registers more properly
The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.
This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).
* Tabs, not spaces, in Makefiles
* util: Fix typos in Async BB Reg Comments
2016-09-16 13:50:09 -07:00
a94b4af92d
Simplify AsyncResetRegVec and make AsyncResetReg companion object
2016-09-16 11:25:10 -07:00
198a2d7022
Merge pull request #302 from ucb-bar/tl2-mmio
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Tl2 mmio
2016-09-15 22:45:35 -07:00
dd19e0911e
tilelink2: handle bus width=1
2016-09-15 22:15:11 -07:00
e1d7f6d7df
PRCI: always use bus width >= XLen
2016-09-15 22:15:07 -07:00
2c53620275
chisel3: bump for Irrevocable(Decoupled) constructor
2016-09-15 21:28:56 -07:00
0e80f7fd0f
HintHandler: don't violate Irrevocable rules
2016-09-15 21:28:56 -07:00
f05222a072
testconfigs: disable atomics until AtomicAbsorber finished
2016-09-15 21:28:56 -07:00
38a9421c75
Comparator: don't compare addr_beat when it's irrelevant
2016-09-15 21:28:56 -07:00
669e3b0d96
Regression: fix-up address lookup
2016-09-15 21:28:56 -07:00
