riscv/rocket-chip
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738 Commits

Author SHA1 Message Date
Andrew Waterman
9c857b83f0 refactor PCR file 2012-11-27 01:28:06 -08:00
Andrew Waterman
64674d4d39 clean up PTW and support PADDR_BITS < VADDR_BITS 2012-11-26 20:38:45 -08:00
Andrew Waterman
608f65e716 don't wastefully read 2x the bits from D$ RAMs 2012-11-26 20:34:30 -08:00
Andrew Waterman
352bb464b5 clock gate X/M and M/W store data registers 2012-11-26 20:33:41 -08:00
Andrew Waterman
8a6ff5f9aa fix D$ writeback bug 
I swear I did this last week... perhaps I am finally losing it!
 2012-11-25 19:46:48 -08:00
Andrew Waterman
de2f28193a get rid of more global constants 2012-11-25 04:24:25 -08:00
Andrew Waterman
c036cdc1ea add option for 2-cycle load-use delay 2012-11-24 22:01:08 -08:00
Andrew Waterman
b514c7b725 clean up I$ parity code 2012-11-24 22:00:43 -08:00
Andrew Waterman
55082e45c4 add AVec, which automatically infers element type 
should consider modifying Vec as such
 2012-11-24 18:19:28 -08:00
Andrew Waterman
2b26082132 use 1r1w ram for tags; merge tags & permissions 
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
 2012-11-20 04:09:26 -08:00
Andrew Waterman
72f94d1141 fix virtual address sign extension detection 2012-11-20 04:06:57 -08:00
Andrew Waterman
30038bda8a bypass stores to subsequent loads 
since we handle subword stores as RMW operations, this occurs frequently
 2012-11-20 01:33:32 -08:00
Yunsup Lee
395e4e3dd6 andrew'x fix for D$ corner case in writeback->abort->probe 2012-11-18 03:11:06 -08:00
Yunsup Lee
06eeb90e2a vector unit interfaces to the new D$ 2012-11-17 20:07:41 -08:00
Yunsup Lee
81d711e892 fix D$ bug; now D$ doesn't respond to prefetches 2012-11-17 20:06:13 -08:00
Andrew Waterman
29bc361d6c remove global constants; disentangle hwacha a bit 2012-11-17 17:24:08 -08:00
Andrew Waterman
5a7777fe4d clock gate integer datapath more aggressively 2012-11-17 06:48:44 -08:00
Andrew Waterman
cc067026a2 pipeline D$ response -> FPU regfile 2012-11-17 06:48:11 -08:00
Andrew Waterman
e68b039133 fix misc. D$ control bugs 2012-11-17 06:47:27 -08:00
Andrew Waterman
dad7b71062 provide cmd/addr with cache response 2012-11-16 21:26:12 -08:00
Andrew Waterman
cb8ac73045 provide store data with cache response 2012-11-16 21:15:13 -08:00
Andrew Waterman
9e010beffe fix D$ refill bug 2012-11-16 21:05:29 -08:00
Andrew Waterman
8dce89703a new D$ with better QoR and AMO pipelining 
Vector unit is disabled because nack handling needs to be fixed.
 2012-11-16 02:39:33 -08:00
Andrew Waterman
a90a1790a5 improve tlb qor 2012-11-16 01:59:38 -08:00
Andrew Waterman
ff8c736d94 move icache invalidate out of request bundle 2012-11-16 01:55:45 -08:00
Andrew Waterman
6d10115b19 fix D$ tag width 2012-11-15 16:46:39 -08:00
Yunsup Lee
be1980dd2d refactored vector queue interface 2012-11-07 01:15:33 -08:00
Yunsup Lee
8764fe786a refactored vector tlb 2012-11-06 23:53:52 -08:00
Yunsup Lee
9a02298f6f andrew's fix for tlb lockup 2012-11-06 23:52:58 -08:00
Andrew Waterman
4d1ca8ba3a remove more global consts; refactor DTLBs 
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
 2012-11-06 08:13:44 -08:00
Andrew Waterman
e76892f758 remove more global constants 2012-11-06 02:55:45 -08:00
Andrew Waterman
c5b93798fb factor out more global constants 2012-11-05 23:52:32 -08:00
Yunsup Lee
ee081d1671 modify code to fix UFix := Bits error 2012-11-05 01:35:55 -08:00
Yunsup Lee
2a25307a8f revamp the vector unit with the new frontend 2012-11-05 01:35:55 -08:00
Andrew Waterman
5b20ed71be move rd=0 check into bypass logic 
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
 2012-11-05 01:30:57 -08:00
Andrew Waterman
5e103054fd fix bug in quine mccluskey 2012-11-05 00:28:25 -08:00
Andrew Waterman
e9eca6a95d refactor I$ config; remove Top class 2012-11-04 16:59:36 -08:00
Andrew Waterman
7380c9fe60 aggressively clock gate int and fp datapaths 2012-11-04 16:40:14 -08:00
Andrew Waterman
bd2d61de03 use 8T SRAM for I$; gate clock more aggressively 2012-11-04 16:39:25 -08:00
Andrew Waterman
fedee6c67d add generic error correcting codes 2012-10-30 01:03:47 -07:00
Andrew Waterman
5773cbb68a rejigger htif to use UncoreConfiguration 2012-10-18 17:26:03 -07:00
Henry Cook
e2eb7ce8e9 Cleanup git incompetence 2012-10-16 16:54:58 -07:00
Henry Cook
88ac5af181 Merged consts-as-traits 2012-10-16 16:32:35 -07:00
Henry Cook
6cff1c13d8 Refer to traits moved to uncore, add UncoreConfiguration to top 2012-10-16 14:22:23 -07:00
Andrew Waterman
b9a2af697d turn off HAVE_VEC as it's currently broken 
the new I$/frontend needs to be integrated
 2012-10-16 07:38:19 -07:00
Andrew Waterman
0a640f2cc6 make DecodeLogic deterministic (hopefully) 2012-10-16 04:51:21 -07:00
Andrew Waterman
5821900329 don't refetch from I$ if on same 16B block 2012-10-16 02:24:38 -07:00
Andrew Waterman
b955985b38 improve divider QoR 2012-10-16 02:24:38 -07:00
Andrew Waterman
197154c485 use BTB for JALR 2012-10-16 02:24:37 -07:00
Andrew Waterman
fc648d13a1 remove old Mux1H; add implicit conversions 2012-10-16 02:24:37 -07:00
Andrew Waterman
661f8e635b merge I$, ITLB, BTB into Frontend 2012-10-16 02:24:37 -07:00
Andrew Waterman
fcd69dba98 add optional early-out to mul/div 2012-10-16 02:24:37 -07:00
Andrew Waterman
27ddff1adb simplify and improve multiplier 2012-10-16 02:24:37 -07:00
Henry Cook
8970b635b2 improvements to implicit RocketConfiguration parameter 2012-10-15 16:29:49 -07:00
Henry Cook
a7a4e65690 Initial verison of reading config from files 2012-10-15 16:05:50 -07:00
Henry Cook
5d2a470215 all rocket-specific arbiters in one file and refactored traits slightly 2012-10-15 16:05:32 -07:00
Huy Vo
1864e41361 memserdes + slowio out of rocket and into uncore 2012-10-10 15:25:24 -07:00
Huy Vo
fe21142972 fixed memdessert unpacking 2012-10-09 13:03:17 -07:00
Henry Cook
9025d0610c first pass at configuration object passed as implicit parameter 2012-10-07 22:37:29 -07:00
Henry Cook
dfdfddebe8 constants as traits 2012-10-07 22:20:03 -07:00
Henry Cook
b5ff436092 decode constant object split into multiple objects 2012-10-05 15:50:42 -07:00
Andrew Waterman
ed8cc4a1cf eliminate D$ probe->WB critical path 2012-10-04 09:05:14 -07:00
Huy Vo
e909093f37 factoring out uncore into separate uncore repo 2012-10-01 16:08:41 -07:00
Henry Cook
b9a9664de5 uncore and rocket changes for new xact types 2012-10-01 10:47:36 -07:00
Huy Vo
d9cb96c0ae factored out common stuff to ChiselUtil 2012-09-27 22:53:34 -07:00
Andrew Waterman
667b4ee858 remove Queue flush port (override reset instead) 2012-08-22 13:39:19 -07:00
Andrew Waterman
d4a001b867 add PriorityMux; use to implement PriorityEncoder 2012-08-22 13:38:25 -07:00
Andrew Waterman
743e032f06 generalize interface to DecodeLogic 2012-08-22 13:38:07 -07:00
Andrew Waterman
0f20771664 rename queue to Queue 
fixes build with case-insensitive file system
 2012-08-08 22:11:59 -07:00
Andrew Waterman
897a4e349b fix some LLC control bugs 2012-08-06 17:10:04 -07:00
Andrew Waterman
e9c35b4923 ameliorate DTLB kill->rdy critical path 2012-08-06 17:05:05 -07:00
Andrew Waterman
b94e6915ab refactor IPIs; use new tohost/fromhost protocol 2012-08-03 19:00:34 -07:00
Andrew Waterman
6510f020c7 fix deadlock in coherence hub 2012-08-03 19:00:03 -07:00
Andrew Waterman
e3726c4db0 fix control bug in LLC 
structural hazard on tag ram caused deadlock
 2012-08-03 18:59:37 -07:00
Andrew Waterman
def913096e pipeline LLC further 2012-07-31 17:45:14 -07:00
Andrew Waterman
3a8f3e0de5 further pipeline the LLC 2012-07-30 20:12:11 -07:00
Andrew Waterman
80c243469e add flow queues and skid buffers 
hopefully they work
 2012-07-30 18:47:12 -07:00
Andrew Waterman
be4fa936dd fix PriorityEncoderOH bug 2012-07-30 18:28:54 -07:00
Andrew Waterman
2ec76390e3 improve PriorityEncoderOH and add Counter util 2012-07-30 16:06:55 -07:00
Yunsup Lee
2af84f994a remove reset pin on llc 2012-07-28 21:14:51 -07:00
Yunsup Lee
0a1cd1175c add reset pin to llc 2012-07-27 18:44:39 -07:00
Huy Vo
db91c4cf6c hwacha 2012-07-27 18:13:20 -07:00
Huy Vo
32a16d183f consts file doesn't depend on WIDTH_PVFB if HAVE_PVFB == false 2012-07-27 18:13:20 -07:00
Andrew Waterman
130fa95ed6 expand HTIF's PCR register space 2012-07-27 14:52:39 -07:00
Andrew Waterman
7778802395 reduce number of outstanding transactions 2012-07-26 14:51:41 -07:00
Andrew Waterman
9c50621a19 remove chip-specific uncore gunk 2012-07-26 03:26:52 -07:00
Andrew Waterman
a5bea4364f memory system bug fixes 2012-07-26 00:05:21 -07:00
Yunsup Lee
3a2b305ddf change htif width to 16 2012-07-25 17:25:50 -07:00
Andrew Waterman
177dbdadd9 merge HTIF port and backup memory port 2012-07-25 00:18:02 -07:00
Yunsup Lee
309193dd07 change llc size 2012-07-24 14:10:29 -07:00
Yunsup Lee
6541cf22a4 fix bug in coherence hub, respect xact_rep.ready 2012-07-23 20:56:55 -07:00
Yunsup Lee
f4e3e72ad1 hoist HTIF_WIDTH out to consts 2012-07-23 17:30:04 -07:00
Andrew Waterman
a21c355114 fix htif split request/response 2012-07-23 17:15:16 -07:00
Andrew Waterman
938effc053 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Yunsup Lee
379f021359 change ioHTIF interface between the tile/uncore boundary to cope with asynchrony 2012-07-22 18:26:02 -07:00
Yunsup Lee
c892950bf1 hoist out uncore as its own component 2012-07-22 17:48:17 -07:00
Huy Vo
0a97d6ab4d type casting 2012-07-18 13:03:35 -07:00
Andrew Waterman
f42c6afed2 decouple all interfaces between tile and top 
also, add an "incoherent" bit to tilelink to indicate no probes needed
 2012-07-17 22:55:40 -07:00
Andrew Waterman
4e44ed7400 allow back pressure on IPI requests 2012-07-17 22:55:40 -07:00
Yunsup Lee
f633a55722 fix dcache tag array size 2012-07-16 22:19:03 -07:00
Andrew Waterman
e496cd7584 use Mem to implement queues to speed things up 2012-07-13 21:48:05 -07:00
Huy Vo
fd95159837 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Andrew Waterman
bac82762d3 use only one (wide) tag ram for set assoc. caches 2012-07-12 14:50:12 -07:00
Andrew Waterman
429fcbed8e fix some LLC bugs 2012-07-11 17:56:39 -07:00
Andrew Waterman
f645fb4dd7 add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
 2012-07-10 05:23:29 -07:00
Andrew Waterman
5035374f36 update to new chisel 2012-07-08 17:59:41 -07:00
Andrew Waterman
39d198ecdc fix htif handling of large memory reads 2012-06-26 19:12:11 -07:00
Andrew Waterman
4e5f874266 update to new chisel/hwacha 2012-06-08 00:13:14 -07:00
Huy Vo
a99cebb483 ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
Huy Vo
04304fe788 moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Huy Vo
c975c21e44 views removed 2012-06-06 12:51:26 -07:00
Andrew Waterman
943b6d0616 remove debug println 2012-06-06 02:48:48 -07:00
Andrew Waterman
7f6319047e update to new scala/chisel/Mem 2012-06-06 02:47:22 -07:00
Huy Vo
7408c9ab69 removing wires 2012-05-24 10:42:39 -07:00
Huy Vo
181b20d69c working vec unit with pvfb 2012-05-24 10:38:14 -07:00
Andrew Waterman
faee45bf4c fix setpcr/clearpcr not writing rd 2012-05-21 07:25:35 -07:00
Yunsup Lee
c9602a0d2e fix vector control decode bug 2012-05-15 10:26:37 -07:00
Gage W Eads
d0bc995c88 Fixed IRQ_IPI -> IRQ_TIMER typo 2012-05-14 22:25:12 -07:00
Andrew Waterman
a2f6d01c1b add programmable coreid register 2012-05-09 03:09:22 -07:00
Andrew Waterman
e0e1cd5d32 add IPIs and an IPI test 
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
 2012-05-08 22:58:00 -07:00
Henry Cook
87cbae2c8a Removed defunct ioDmem 2012-05-07 17:31:39 -07:00
Andrew Waterman
b851f1b34c support maximum-MTU HTIF packets 2012-05-03 21:11:43 -07:00
Andrew Waterman
171c87002e reduce HTIF clock divider for now 2012-05-03 04:21:11 -07:00
Andrew Waterman
e1f9dc2c1f generalize page table walker 
also, don't instantiate vitlb when !HAVE_VEC
 2012-05-03 02:29:09 -07:00
Andrew Waterman
2d4e5d3813 fix pseudo-LRU verilog generation bug 2012-05-02 19:31:31 -07:00
Henry Cook
622a801bb1 Refactored cpu/cache interface to use nested bundles 2012-05-02 11:54:28 -07:00
Andrew Waterman
65ff397122 improved instruction decoding 
it now makes use of don't-cares by performing logic minimization
 2012-05-01 20:16:36 -07:00
Andrew Waterman
4cfa6cd9a8 force Top.main's return type to Unit 2012-05-01 19:55:16 -07:00
Andrew Waterman
5819beed64 use parameterized FP units 2012-05-01 01:25:43 -07:00
Andrew Waterman
eafdffe125 simplify page table walker; speed up emulator 2012-05-01 01:24:36 -07:00
Andrew Waterman
c13d3e6f88 fix probe tag read-modify-write atomicity violation 2012-04-26 02:29:31 -07:00
Andrew Waterman
66f86a2194 use pseudo-LRU replacement for TLBs 2012-04-26 02:29:30 -07:00
Andrew Waterman
a0378c5d2f remove faulting TLB entry after page fault 
this vastly reduces the frequency with which the TLB must be flushed
 2012-04-26 02:29:30 -07:00
Andrew Waterman
6d8fc74378 fix DTLB permissions bug 2012-04-26 02:29:30 -07:00
Henry Cook
1ed89f1cab Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle 2012-04-24 17:17:42 -07:00
Henry Cook
55e86b5cf4 Fixed coherence bug: probe counting for single tile 2012-04-24 17:17:13 -07:00
Henry Cook
a39080d0b1 Fixed abort bug: xact_abort.ready was not pinned high 2012-04-24 17:16:40 -07:00
Andrew Waterman
fb4408b150 fix AMO replay/coherence deadlock 2012-04-15 22:56:02 -07:00
Andrew Waterman
724735f13f fix writeback bug 2012-04-13 03:16:48 -07:00
Andrew Waterman
00d934cfac fix coherence bugs in cache 2012-04-12 21:57:37 -07:00
Henry Cook
fef58f1b3a Policy determined by constants. MSI policy added. 2012-04-11 17:56:59 -07:00
Andrew Waterman
c0ec3794bf coherence mostly works now 2012-04-10 02:22:45 -07:00
Henry Cook
3cdd166153 Refactored coherence as member rather than trait. MI and MEI protocols. 2012-04-10 00:09:58 -07:00
Henry Cook
9c8f849f50 defined abstract coherence traits in base trait, added Incoherent trait, cleaned up incoherent policy 2012-04-09 23:29:32 -07:00
Henry Cook
551e09c9d5 changed coherence type width names to represent max sizes for all protocols 2012-04-09 23:29:32 -07:00
Henry Cook
0b4937f70f changed coherence message type names 2012-04-09 23:29:31 -07:00
Henry Cook
ed79ec98f7 Refactored coherence better from uncore hub, better coherence function names 2012-04-09 23:29:31 -07:00
Andrew Waterman
aee9378712 fix coherence bug with multiple probe replies 2012-04-09 21:40:35 -07:00
Huy Vo
c9c3bd02bc kill mem stage if fpu nacks in mem stage 2012-04-01 17:02:32 -07:00
Andrew Waterman
7f254d9670 refine FP bugfixes 2012-04-01 14:52:33 -07:00
Huy Vo
c7c35322c2 two bug fixes to fpu 2012-03-31 22:23:51 -07:00
Andrew Waterman
a09e8d1c55 remove I$ prefetcher for now 
there's a bug in it, and I don't have time to fix it at the moment.
 2012-03-27 15:43:56 -07:00
Andrew Waterman
452876af37 fence on vvcfg; implement fence.v.g correctly 2012-03-27 14:49:00 -07:00
Yunsup Lee
bb704dc0c9 fix vector length calc bug, thanks chris and andrew 2012-03-27 12:04:07 -07:00
Andrew Waterman
6bda8674bd no dessert tonight :( 2012-03-26 23:50:09 -07:00
Yunsup Lee
a70f0414fa fix a workaroundable bug 2012-03-26 20:51:54 -07:00
Yunsup Lee
32d95e9594 fix -1:0 index problem for direct map case 2012-03-26 17:00:01 -07:00
Andrew Waterman
e2fe525fb6 remove bug from dessert 2012-03-26 14:18:57 -07:00
Yunsup Lee
e6b0e565de turn HAVE_VEC on 2012-03-26 01:21:39 -07:00
Andrew Waterman
5f53cd4ac1 reduce HTIF width 2012-03-25 23:49:59 -07:00
Andrew Waterman
ef505de017 reduce HTIF width 2012-03-25 23:49:45 -07:00
Andrew Waterman
31f0b600fd add dessert 2012-03-25 23:03:20 -07:00
Andrew Waterman
1666d3fbd7 loop host.in to host.out during reset 2012-03-25 21:45:10 -07:00
Andrew Waterman
f62a02ab54 remove dumb stuff in top.scala 2012-03-25 21:30:01 -07:00
Andrew Waterman
88bf8a4f23 add mem serdes unit 2012-03-25 17:03:58 -07:00
Andrew Waterman
7fa93da4f5 add backup memory port (disabled for now) 2012-03-25 15:49:32 -07:00
Yunsup Lee
1f33f6bb58 HAVE_VEC is on 2012-03-24 20:54:43 -07:00
Andrew Waterman
86d56ff67b refactor cpu/i$/d$ into Tile (rather than Top) 2012-03-24 16:57:28 -07:00
Andrew Waterman
3a487ac89b improve htif<->pcr interface 2012-03-24 16:57:28 -07:00
Andrew Waterman
54fa6f660d new supervisor mode 2012-03-24 13:03:31 -07:00
Yunsup Lee
65929a62e3 fix reset value for appvl 2012-03-22 15:32:04 -07:00
Yunsup Lee
aaed0241af get rid of vxcptwait 2012-03-21 15:09:04 -07:00
Yunsup Lee
023734175d now fence stalls in decode 2012-03-20 17:10:05 -07:00
Yunsup Lee
e450e3aa40 fix irt counter bug regarding vector stuff 2012-03-20 17:09:54 -07:00
Yunsup Lee
7d7d7f49f9 change the tlb arbiter to a round robing one 2012-03-20 15:21:36 -07:00
Yunsup Lee
1cddd5de56 fix amo locking up problem 2012-03-20 02:16:28 -07:00
Yunsup Lee
56cb9b7a63 fix bug in coherence hub, specifically in abort handling logic 2012-03-20 02:16:28 -07:00
Yunsup Lee
c036fff79c fix id interrupt signal 2012-03-19 15:13:57 -07:00
Yunsup Lee
0edea00166 now HAVE_VEC is true, since it passes the emulator 2012-03-19 03:10:00 -07:00
Yunsup Lee
264732556f fixes to match verilog X semantics 2012-03-19 03:10:00 -07:00
Andrew Waterman
bd27d0fab2 can now take interrupts on stalled instructions 2012-03-19 01:02:06 -07:00
Andrew Waterman
2ed0be65f9 fix RRArbiter 2012-03-19 00:19:33 -07:00
Yunsup Lee
ba06cd953e add chosen 2012-03-18 20:43:17 -07:00
Andrew Waterman
c4a91303fb update vector fence names and encoding 2012-03-18 20:42:38 -07:00
Yunsup Lee
2a01f558ba fix unmasked valid bug in ctrl_vec 2012-03-18 19:55:24 -07:00
Yunsup Lee
98e10ddc3c update vector exception instructions 2012-03-18 16:36:12 -07:00
Yunsup Lee
7493d55d3f add pf fault handling 2012-03-18 15:06:39 -07:00
Yunsup Lee
62ada5ea9e hookup vitlb ptw port 2012-03-17 23:01:06 -07:00
Yunsup Lee
b793d63182 no vector interrupt masking 2012-03-17 23:01:06 -07:00
Yunsup Lee
8a4f95e617 changes to xcpt handling 2012-03-17 17:50:37 -07:00
Yunsup Lee
8c50c81b81 drop vec_irq_aux pcr register, now everything goes through badvaddr 2012-03-17 14:03:57 -07:00
Yunsup Lee
3b4680a834 add vitlb exception port 2012-03-17 14:03:33 -07:00
Andrew Waterman
a47eeb9571 retime D$ bypass into beginning of EX stage 2012-03-16 18:35:54 -07:00
Andrew Waterman
6c26921766 reduce D$ critical path through page table walker 
costs an extra cycle per page table level to resolve a TLB miss. too bad.
 2012-03-16 18:35:54 -07:00
Yunsup Lee
d38603a4ee change number of tlb entries 2012-03-16 17:08:03 -07:00
Andrew Waterman
f0157b9e2a fix coherence bug 
popping wrong store dependence queue
 2012-03-16 01:24:07 -07:00
Andrew Waterman
cfca2d1411 clean up cache interfaces; avoid reserved keywords 2012-03-16 00:44:16 -07:00
Andrew Waterman
820884c7e6 fix probes for smaller cache sizes 
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
 2012-03-15 23:08:30 -07:00
Andrew Waterman
4684171ac6 fix fence.i for associative caches 2012-03-15 21:23:21 -07:00
Andrew Waterman
2b0bc8df2b use divided clk for htif. UDPATE YOUR FESVR 
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
 2012-03-15 18:36:51 -07:00
Yunsup Lee
ba566f246e change icache parameters 2012-03-15 15:35:12 -07:00
Yunsup Lee
72006160dc fix vxcptwait inst bug, it was incorrect when exception_valid was on before do_xcptwait 2012-03-15 02:10:21 -07:00
Yunsup Lee
f972977da1 refactored VMU, now uses one skid buffer 2012-03-15 01:10:17 -07:00
Henry Cook
b5fa86e844 4-way associative by default 2012-03-14 17:51:12 -07:00
Andrew Waterman
7dde7099d2 use broadcast hub and coherent HTIF 2012-03-14 16:44:35 -07:00
Yunsup Lee
b19d783fbd add vector irq handler 2012-03-14 14:15:28 -07:00
Yunsup Lee
040d62f372 refactored vector exception handling interface 2012-03-13 23:45:34 -07:00
Yunsup Lee
b100544b25 datapath to read out vector state 2012-03-13 23:45:34 -07:00
Yunsup Lee
5655dbd5da add vvcfg and vtcfg instructions 2012-03-13 23:45:34 -07:00
Andrew Waterman
ab6c9350db fix minor coherence bugs 2012-03-13 19:10:54 -07:00
Andrew Waterman
1788c34113 parameterize broadcast hub by # of tiles 2012-03-13 17:12:01 -07:00
Andrew Waterman
1492457df5 add probe replies to HTIF 2012-03-13 16:56:47 -07:00
Andrew Waterman
b0f798962c add probe unit 2012-03-13 16:43:51 -07:00
Huy Vo
fdffb124e3 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-13 12:34:39 -07:00
Huy Vo
6fd1527476 fix to rocket vec_dpath, updating makefiles to run xcpt test cases 2012-03-13 12:34:02 -07:00
Henry Cook
287bc1c262 Further refinement of tag_match/tag_hit signals 2012-03-13 11:48:12 -07:00
Andrew Waterman
d76b05bde1 fix way selection on D$ write upgrades 2012-03-13 02:21:02 -07:00
Andrew Waterman
fd29e00db0 support non-power-of-2 queue sizes 
need to manually wrap queue pointers.
 2012-03-13 01:58:28 -07:00
Henry Cook
cbf7b13341 fix hit logic for amos 2012-03-12 22:01:52 -07:00
Henry Cook
6229a33dc4 fixed cache controller flush unit deadlock 2012-03-12 22:01:52 -07:00
Henry Cook
ea0775643b fixed abort bug 2012-03-12 22:01:52 -07:00
Yunsup Lee
1ba5e7b865 changes to the vector exception interface 2012-03-11 21:38:47 -07:00
Yunsup Lee
113a94a21d add vector hold waits 2012-03-11 16:29:19 -07:00
Yunsup Lee
e42a4c767e don't stall on vector fences, keep replaying 2012-03-11 16:29:19 -07:00
Henry Cook
c5dd37ae80 bugfix in locking arbiter 2012-03-11 15:47:27 -07:00
Henry Cook
4ebf637642 More broadcast hub bugfixes 2012-03-11 14:17:27 -07:00
Henry Cook
a4d0025187 fix icache prefetch global_xact_id bug 2012-03-11 00:50:11 -08:00
Yunsup Lee
1aa4b0e93d going back to null coherence hub 2012-03-10 20:16:20 -08:00
Andrew Waterman
8ffdac9526 fix D$ store-upgrade bug 
loads to the same address as stores that cause an upgrade
could return the old value
 2012-03-10 15:50:10 -08:00
Andrew Waterman
4f4b990a4f fix null hub store ack bug 2012-03-10 15:19:12 -08:00
Yunsup Lee
44ff22a26f vector exception handler now handles prefetches correctly 2012-03-10 12:54:36 -08:00
Andrew Waterman
7eb73c325e fix signedness of zero fmul results 
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0.  Now we
add -0.0 if rs1*rs2 is negative.
 2012-03-10 00:21:51 -08:00
Andrew Waterman
e3a68848e0 fix D$ critical paths and fix verilog build 2012-03-09 20:02:51 -08:00
Henry Cook
e591d83e91 Fixed global_xact_id propagation bug 2012-03-09 11:05:44 -08:00
Henry Cook
9319130483 Special cased NTILES == 1 due to log2up revision 2012-03-09 11:04:58 -08:00
Andrew Waterman
85504f0ddc fix bug in fence.i and improve test 2012-03-09 03:26:05 -08:00
Andrew Waterman
766bac88f8 refactor D$ writebacks and flushes 
MSHRs now arbitrate for writebacks and handle flushes.
 2012-03-09 02:55:46 -08:00
Andrew Waterman
ff2e47f380 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Yunsup Lee
a1b30282dd major refactoring on vector exception interface 2012-03-09 01:09:22 -08:00
Yunsup Lee
8acbe98f53 change how fence.*.cv works, now control processor stalls on the fence instruction 2012-03-08 23:32:31 -08:00
Henry Cook
22726ae646 icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data 2012-03-08 18:47:32 -08:00
Henry Cook
4d2e7172f6 Added require_ack field to TransactionReply bundle 2012-03-08 18:07:44 -08:00
Henry Cook
35c4bd4084 Hub addr comparison bug fix 2012-03-08 16:39:05 -08:00
Henry Cook
788ad327da Fixed dependency queue bug in Broadcast Hub 2012-03-08 11:36:10 -08:00
Henry Cook
7f43dee0c9 PriorityEncoder apply() no longer has recursive depth param 2012-03-08 01:04:26 -08:00
Andrew Waterman
5a7c5772a8 clearly distinguish PPN and cache tag 2012-03-07 23:11:17 -08:00
Andrew Waterman
941873bad1 coherence hub fixes 2012-03-07 21:03:44 -08:00
Henry Cook
7deff5fbe2 Broadcast hub bug fixes for load uncached mem req and store uncached xact rep 2012-03-07 11:40:49 -08:00
Andrew Waterman
c09eeb7fd2 fix D$ next-state logic 
it was using the CPU command from the wrong pipeline stage,
which was a don't-care with ThreeStateIncoherence.
 2012-03-07 01:42:08 -08:00
Andrew Waterman
a0c9452b86 change D$ to use FourStateCoherence protocol 
instead of ThreeStateIncoherence.
 2012-03-07 01:26:35 -08:00