When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.
This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
If user compiles without +define+DEBUG but then requests +vcdfile at
simulation time, that request would be silently ignored. This changes
it to a fatal error.
It's good philosophy to treat plusargs like +vcdfile as commands, not
suggestions, and die immediately if they cannot be honored, instead of
silently ignoring them. Otherwise the user sits through the entire
simulation and then is left scratching his head wondering where his
waveforms are.
This fixes the following compile warnings and simulation errors:
Compile-time warnings:
$vcdplusfile(vcdplusfile);
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ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): Unrecognized system task or function: $vcdplusfile (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
$vcdpluson(0);
|
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): Unrecognized system task or function: $vcdpluson (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
$vcdplusmemon(0);
|
ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): Unrecognized system task or function: $vcdplusmemon (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
`VCDPLUSCLOSE
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ncelab: *W,MISSYST (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): Unrecognized system task or function: $vcdplusclose (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
Which then become simulation-time errors:
$vcdplusfile(vcdplusfile);
|
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,42|17): User Defined system task or function ($vcdplusfile) registered during elaboration and used within the simulation has not been registered during simulation.
$vcdpluson(0);
|
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,43|15): User Defined system task or function ($vcdpluson) registered during elaboration and used within the simulation has not been registered during simulation.
$vcdplusmemon(0);
|
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,44|18): User Defined system task or function ($vcdplusmemon) registered during elaboration and used within the simulation has not been registered during simulation.
`VCDPLUSCLOSE
|
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,89|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
`VCDPLUSCLOSE
|
ncsim: *E,MSSYSTF (/home/scottj/rocket-chip/vsrc/TestDriver.v,97|20): User Defined system task or function ($vcdplusclose) registered during elaboration and used within the simulation has not been registered during simulation.
The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random
function) says: "The seed argument shall be an integral variable."
This fixes the following compile warning:
rand_value = $random($urandom);
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ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue.
When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
