Yunsup Lee
1a09e46f69
Merge branch 'master' into fix-addrmap-error-msg
2016-09-19 18:08:58 -07:00
Yunsup Lee
15e7041ccb
Merge pull request #316 from ucb-bar/dynamic-reset-vector
...
Allow reset vector to be set dynamically
2016-09-19 18:00:25 -07:00
Andrew Waterman
3b38736a8e
Make BaseTopModule and BaseTopModule abstract
...
They aren't meant to be directly instantiated.
2016-09-19 17:18:35 -07:00
Andrew Waterman
d0572d6aab
Allow reset vector to be set dynamically
...
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins. Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.
Additionally, allow MTVEC to *not* be reset. In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does. So the reset value is superfluous.
2016-09-19 17:18:03 -07:00
Andrew Waterman
e6c1bcfedd
Expose carry-out bits from WideCounter
2016-09-19 15:54:17 -07:00
Yunsup Lee
1b26d78114
correctly print out the addrmap overlapping error message
2016-09-19 13:34:58 -07:00
Andrew Waterman
f0debb89e4
Merge pull request #314 from ucb-bar/widecounter-reset
...
Allow WideCounter to not be reset
2016-09-18 22:37:40 -07:00
Andrew Waterman
a49814c667
Allow WideCounter to not be reset
2016-09-18 18:45:51 -07:00
Wesley W. Terpstra
aa956c0108
Merge pull request #312 from ucb-bar/tl2-cheap-address-decode
...
Tl2 cheap address decode
2016-09-17 17:37:03 -07:00
Wesley W. Terpstra
9817a00ed9
tilelink2: Fuzzer should check address validity before injection
2016-09-17 17:07:21 -07:00
Wesley W. Terpstra
b11839f5a1
tilelink2: differentiate fast/safe address lookup cases
2016-09-17 17:04:18 -07:00
Wesley W. Terpstra
b4baae4214
tilelink2: minimize Xbar decode logic
2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
76d8ed6a69
tilelink2: remove 'strided'; !contiguous is clearer
2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
fa0f119f3c
tilelink2: consider the implications of negative address mask
2016-09-17 16:14:22 -07:00
Wesley W. Terpstra
e437508548
tilelink2: track interrupt connectivity like in TL2
2016-09-17 14:43:48 -07:00
Wesley W. Terpstra
fd3ac4653c
Merge pull request #311 from ucb-bar/rom-executable
...
Rom executable
2016-09-17 01:28:52 -07:00
Wesley W. Terpstra
01c1886b9d
Utils: cacheable only if there is a cache manager
2016-09-17 00:56:21 -07:00
Wesley W. Terpstra
6c3269a1d8
SRAM: optionally (default: true) executable
2016-09-17 00:19:37 -07:00
Wesley W. Terpstra
e749558190
ROM: optionally (default: true) executable
2016-09-17 00:19:09 -07:00
Wesley W. Terpstra
c70045b8b3
Utils: express cacheability from TL2 to TL1
2016-09-17 00:16:40 -07:00
Wesley W. Terpstra
e3d2bd3323
Top: print memory region properties, RWX [C]
2016-09-17 00:16:00 -07:00
Wesley W. Terpstra
75c73fce37
Merge pull request #309 from ucb-bar/tl2-addrmap
...
Tl2 addrmap
2016-09-16 19:09:22 -07:00
Wesley W. Terpstra
5c858685aa
Utils: support managers with multiple addresses
2016-09-16 18:03:49 -07:00
Wesley W. Terpstra
a9382b3116
Periphery: test bench looks for "testram"
2016-09-16 17:47:20 -07:00
Wesley W. Terpstra
b5ce6150c7
Periphery: dynamically create address map + config string for TL2
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
8876d83640
Prci: preserve Andrew's preferred clint name
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
a357c1d42e
tilelink2: create DTS for devices automagically
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
2587234838
tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
915a929af1
tilelink2: Nodes can now mix context into parameters
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
503ce14c98
Merge pull request #307 from ucb-bar/address-shrink
...
RR: undefined regs return zeros
2016-09-16 16:55:35 -07:00
Wesley W. Terpstra
dae0918c85
tilelink2 RegisterRouter: support undefZero
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
f0f553f227
tilelink2 RegisterRouterTest: work around firrtl warning
...
Using io.wready leads to verilog that reads from the output...
Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
Port "io_wready" declared as output in module "RRTestCombinational_29" may
need to be inout. Coercing to inout.
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
3fcc1a4460
tilelink2 RegisterRouterTest: don't couple fire into helpers
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
2210e71f42
tilelink2 AddressDecoder: validate output of optimization
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
023a54f122
tilelink2 AddressDecoder: improved heuristic
2016-09-16 16:09:00 -07:00
Yunsup Lee
4abba87b61
bump firrtl to include empty module fix for vivado ( #306 )
2016-09-16 15:53:53 -07:00
Andrew Waterman
86b70c8c59
Rename PRCI to CoreplexLocalInterrupter
...
That's all it's doing (there wasn't much PRC).
2016-09-16 14:26:34 -07:00
Wesley W. Terpstra
4b1de82c1d
RegField: separate UInt=>bytes and bytes=>regs
2016-09-16 14:24:28 -07:00
Wesley W. Terpstra
943c36954d
tilelink2 RegField: .bytes should update more than one byte!
2016-09-16 14:24:24 -07:00
Andrew Waterman
6134384da4
Fix deprecation warnings
2016-09-16 14:24:19 -07:00
mwachs5
a031686763
util: Do BlackBox Async Set/Reset Registers more properly ( #305 )
...
* util: Do Set/Reset Async Registers more properly
The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.
This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).
* Tabs, not spaces, in Makefiles
* util: Fix typos in Async BB Reg Comments
2016-09-16 13:50:09 -07:00
Andrew Waterman
a94b4af92d
Simplify AsyncResetRegVec and make AsyncResetReg companion object
2016-09-16 11:25:10 -07:00
Yunsup Lee
198a2d7022
Merge pull request #302 from ucb-bar/tl2-mmio
...
Tl2 mmio
2016-09-15 22:45:35 -07:00
Wesley W. Terpstra
dd19e0911e
tilelink2: handle bus width=1
2016-09-15 22:15:11 -07:00
Wesley W. Terpstra
e1d7f6d7df
PRCI: always use bus width >= XLen
2016-09-15 22:15:07 -07:00
Wesley W. Terpstra
2c53620275
chisel3: bump for Irrevocable(Decoupled) constructor
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
0e80f7fd0f
HintHandler: don't violate Irrevocable rules
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
f05222a072
testconfigs: disable atomics until AtomicAbsorber finished
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
38a9421c75
Comparator: don't compare addr_beat when it's irrelevant
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
669e3b0d96
Regression: fix-up address lookup
2016-09-15 21:28:56 -07:00