riscv/rocket-chip
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1083 Commits

Author SHA1 Message Date
Yunsup Lee bfd0ae125e upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache 2012-02-26 23:46:51 -08:00
Andrew Waterman 6e706c7c74 fix yet another AMO-related replay bug 2012-02-26 20:20:45 -08:00
Andrew Waterman e12b9eae93 remove ext_mem interface 
hindsight is 20/20
 2012-02-26 18:53:39 -08:00
Andrew Waterman 2d04664a98 simplify cpu-cache interface 2012-02-26 18:26:29 -08:00
Andrew Waterman ad713a5d83 fix icache ram depth; new chisel 2012-02-26 17:51:46 -08:00
Yunsup Lee f3bb02b2ea refactored dmem arbiter 2012-02-26 17:38:08 -08:00
Huy Vo 93f41d3359 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Huy Vo 5b0f7ccf68 updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit 2012-02-26 17:24:08 -08:00
Yunsup Lee 766a039ffe small changes to the dtlb arbiter 2012-02-26 16:19:50 -08:00
Daiwei Li 69260756bd change ppn and vpn in dtlb from ufix to bits 2012-02-26 02:54:31 -08:00
Yunsup Lee 49efe4b744 now vu steals cycles from the fpu's fma alu 2012-02-26 01:55:07 -08:00
Daiwei Li 47dbc2a417 head should be working again 2012-02-26 00:30:50 -08:00
Daiwei Li 569698b824 dtlb now arbitrates between cpu, vec, and vec pf 2012-02-25 22:05:30 -08:00
Yunsup Lee 94ba32bbd3 change package name and sbt project name to rocket 2012-02-25 17:09:26 -08:00
Yunsup Lee 946e0c6e4e add vector exception infrastructure 2012-02-25 16:37:56 -08:00
Yunsup Lee 3839e3a318 massive refactoring of vector constants 2012-02-25 15:55:36 -08:00
Henry Cook 3980120279 More stylish bundle param names, some hub progress 2012-02-25 15:27:53 -08:00
Henry Cook db6d480778 Better foldR 2012-02-25 15:27:09 -08:00
Henry Cook df97de0fd3 Better abstraction of data bundles 2012-02-25 12:57:01 -08:00
Henry Cook 4fa31b300b Added popcount util 2012-02-25 12:57:01 -08:00
Yunsup Lee a1600d95db fix bug related to waddr and wdata in wb stage 
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
 2012-02-25 12:21:10 -08:00
Yunsup Lee 137fd62007 refactor cpfences 2012-02-25 12:20:36 -08:00
Andrew Waterman 4121fb178c clean up mul/div interface; use VU mul if HAVE_VEC 2012-02-24 19:22:35 -08:00
Andrew Waterman b3a3289d34 fix (?) external memory request nack interface 2012-02-24 01:42:33 -08:00
Daiwei Li 477f3cde02 added prefetch queues for vu 2012-02-24 00:44:13 -08:00
Yunsup Lee 63939efd0c fix ctrl vec iface hookup - final 2012-02-23 23:03:44 -08:00
Yunsup Lee bf1e643913 fix ctrl vec iface hookup 2012-02-23 22:55:25 -08:00
Andrew Waterman 7b3cce79e3 allocate a primary miss on a prefetch 2012-02-23 22:40:24 -08:00
Yunsup Lee 2ea309cf80 bug fixes to ctrl_vec 2012-02-23 22:35:05 -08:00
Yunsup Lee 91a0bb6f61 add vector prefetch queues 2012-02-23 22:30:38 -08:00
Andrew Waterman 012028efaa fix fpga build 2012-02-23 22:19:38 -08:00
Henry Cook 52da831aa3 finished xact_finish and xact_abort transactors in coherence hub 2012-02-23 18:12:50 -08:00
Henry Cook 1c1ce7d60b finished xact_rep transactor in coherence hub 2012-02-23 17:50:02 -08:00
Andrew Waterman 5332bab6f1 expose FMA ports outside of FPU (for the VU) 2012-02-23 17:39:34 -08:00
Andrew Waterman 6ceaa0e80a correct and simplify replay_next logic 2012-02-23 16:52:52 -08:00
Andrew Waterman f939088be1 move datapath control signals into control unit 
because that's where control signals go
 2012-02-23 16:52:52 -08:00
Yunsup Lee e53792a1eb fix bug in rocket's vector datapath related to wakeup 2012-02-23 10:14:14 -08:00
Andrew Waterman 7c929afe2b HTIF now controls CPU reset 2012-02-22 19:30:03 -08:00
Andrew Waterman 3eebf40310 nack CPU requests during any replay 2012-02-22 18:37:13 -08:00
Henry Cook 62837537f4 Improved TileIO organization, beginnings of hub implementation 2012-02-22 18:24:52 -08:00
Henry Cook 24a32c2811 Refining tilelink interface 2012-02-22 12:15:47 -08:00
Henry Cook 18bd0c232b Added coherence message type enums 2012-02-22 12:15:47 -08:00
Daiwei Li 22f8dd0994 Hook up resp_type to vector unit 2012-02-21 18:20:32 -08:00
Andrew Waterman cfd79c731b add resp_type to ext_mem interface 2012-02-21 17:42:00 -08:00
Andrew Waterman 9a80adef50 only instantiate VI$ if HAVE_VEC 2012-02-21 15:53:19 -08:00
Andrew Waterman c8f768c8b3 fix AMO replay bug 
like the recent AMO bug fix, but affects stores too.  oops.
 2012-02-21 14:39:54 -08:00
Andrew Waterman d5608b2728 fix AMO replay bug 
didn't check for structural hazard on AMO unit
if a replay was initiated one cycle before before
a hit-under-miss AMO was issued
 2012-02-21 01:02:16 -08:00
Andrew Waterman 6135615104 unify cache backend interfaces; generify arbiter 2012-02-20 00:51:48 -08:00
Andrew Waterman 7034c9be65 new htif protocol and implementation 
You must update your fesvr and isasim!
 2012-02-19 23:15:45 -08:00
Andrew Waterman 9af86633d7 invalidate I$ prefetcher when invalidating I$ 2012-02-17 17:56:01 -08:00