6472d4c245
Print Verilator random seed when +verbose is passed
2016-10-04 22:29:39 -07:00
2ab61f1a71
Chisel implicit clock is now named clock, not clk
2016-09-21 16:16:47 -07:00
9e2b0aad65
Revert "allow MODEL to be something other than TestHarness"
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This reverts commit bf253aaa97
2016-09-15 11:53:05 -07:00
bf253aaa97
allow MODEL to be something other than TestHarness
2016-09-14 20:51:56 -07:00
cd12fd1cbb
fix clang support for emulator-debug
2016-09-14 12:20:37 -07:00
cf3c6fa277
add STOP_COND to emulator & match vsim PRINTF_COND
2016-09-09 11:07:17 -07:00
35fbbfc70d
put test harness on the heap in emulator
2016-08-16 14:50:40 -07:00
ed827678ac
Write test harness in Chisel
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This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
9751ea0f35
Fix Verilator VCD ( #157 )
2016-07-09 02:37:39 -07:00
2d44be747a
Fix groundtest without HTIF
2016-06-23 12:17:26 -07:00
30331fcaeb
Remove HTIF; use debug module for testing in simulation
2016-06-23 00:32:05 -07:00
4a8e6c773a
Fix +verbose flag for verilator
2016-06-17 21:09:08 -07:00
99b257316e
replace emulator with verilator for chisel3
2016-06-08 02:43:54 -07:00
46bbbba5e6
New address map
2016-04-30 20:59:36 -07:00
1f211b37df
WIP on new memory map
2016-04-27 14:57:54 -07:00
6fc1e92708
add option to print cycle count regardless of exit status
2015-12-04 12:04:13 -08:00
bbf14ddc01
use definitions in consts header whenever possible
2015-11-05 10:48:32 -08:00
ba5a6af05c
correctly stripe data across memory channels in simulation
2015-11-05 10:48:32 -08:00
dcef020ca0
get multichannel simulation working in emulator
2015-11-05 10:48:32 -08:00
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
9dabcab9c2
Get rid of MemIO in Top and replace with AXI throughout
2015-11-05 10:48:32 -08:00
38a9b23ce7
add a flag to only log and dump after a certain number of cycles
2015-09-22 10:32:31 -07:00
4496e8d4e2
make sure htif_emulator properly sets memory size
2015-09-22 10:32:31 -07:00
0ac6172525
Add "-memsize" flag to emulator
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- Allow user to set memory size (in MiB) used by emulator.
- if memory is exhausted, warn user about memory shortage.
Close #3
2015-08-26 17:53:37 -07:00
d3ccec1044
Massive update containing several months of changes from the now-defunct private chip repo.
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* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
1cfd9f5a0e
add LICENSE
2014-09-12 10:15:04 -07:00
275b72368b
add CONFIG to the name of simulator executable
2014-09-11 22:11:58 -07:00
c03c09ec31
update for rocket-chip release
2014-08-31 20:26:55 -07:00
7f23257873
Print out random seed if test fails
2014-03-17 15:35:32 -07:00
d055c0ebaf
Push rocket/hardfloat/chisel
2014-03-04 16:39:06 -08:00
dfc13236d1
Linux works again!
2014-01-16 12:44:29 -08:00
ab6cd9c9e8
Update chisel, rocket
2013-12-09 15:09:48 -08:00
c55eee7244
Pass target machine exit code back to host OS
2013-10-29 13:24:09 -07:00
fbdbb01232
update to new isa; disable vector tests
2013-09-12 17:04:03 -07:00
ae0716fb6d
Use chisel printf for logging
2013-06-13 10:53:23 -07:00
cfa86dba4f
add FPGA test bench
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The memory models now support back pressure on the response.
2013-05-02 04:59:32 -07:00
d2e1828714
gracefully kill htif thread, fixing tty stuff
2013-05-02 04:59:32 -07:00
def11e44b8
don't pipe stdout to vcd2vpd
2013-03-25 17:01:13 -07:00
c6695bee7c
fix emulator HTIF interface bug
2013-02-20 16:11:21 -08:00
dbb61306f0
randomize coreid mapping
2013-01-26 16:13:14 -08:00
4077b22929
include fesvr as a library; improve harnesses
2013-01-24 23:57:23 -08:00
d911e635d6
simplify c++ memory models; support +dramsim flag
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works for both vlsi and emulator
2012-12-04 07:04:26 -08:00
6d47d18c2b
catch sigterm to gracefully exit (fixes vcd)
2012-11-20 05:40:44 -08:00
b58214d7e3
remove more global constants
2012-11-17 17:25:43 -08:00
cf05b604b3
upgrade to new rocket; improve vlsi makefiles
2012-11-17 07:21:29 -08:00
e2afae011a
factor out global constants
2012-11-06 08:18:40 -08:00
4ed2d614a2
update to new rocket; retime fpu in dc-syn
2012-11-04 16:43:02 -08:00
edf0eeed01
integrate updated rocket/uncore
2012-10-18 17:51:41 -07:00
5d75ddc553
Added dramsim2 memory model to the emulator backend
2012-10-14 14:06:28 -07:00
93a0182b96
everything to get emulator working
2012-10-01 19:30:11 -07:00
