ed827678ac
This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
138 lines
2.9 KiB
C++
138 lines
2.9 KiB
C++
// See LICENSE for license details.
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#include "verilated.h"
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#if VM_TRACE
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#include "verilated_vcd_c.h"
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#endif
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#include <fesvr/dtm.h>
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#include <iostream>
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#include <fcntl.h>
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#include <signal.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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extern dtm_t* dtm;
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static uint64_t trace_count = 0;
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bool verbose;
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void handle_sigterm(int sig)
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{
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dtm->stop();
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}
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double sc_time_stamp()
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{
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return trace_count;
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}
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extern "C" int vpi_get_vlog_info(void* arg)
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{
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return 0;
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}
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int main(int argc, char** argv)
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{
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unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid();
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uint64_t max_cycles = -1;
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uint64_t start = 0;
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int ret = 0;
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FILE *vcdfile = NULL;
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bool print_cycles = false;
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for (int i = 1; i < argc; i++)
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{
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std::string arg = argv[i];
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if (arg.substr(0, 2) == "-v") {
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const char* filename = argv[i]+2;
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vcdfile = strcmp(filename, "-") == 0 ? stdout : fopen(filename, "w");
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if (!vcdfile)
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abort();
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} else if (arg.substr(0, 2) == "-s")
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random_seed = atoi(argv[i]+2);
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else if (arg == "+verbose")
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verbose = true;
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else if (arg.substr(0, 12) == "+max-cycles=")
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max_cycles = atoll(argv[i]+12);
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else if (arg.substr(0, 7) == "+start=")
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start = atoll(argv[i]+7);
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else if (arg.substr(0, 12) == "+cycle-count")
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print_cycles = true;
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}
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srand(random_seed);
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srand48(random_seed);
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Verilated::randReset(2);
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VTestHarness tile;
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#if VM_TRACE
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Verilated::traceEverOn(true); // Verilator must compute traced signals
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std::unique_ptr<VerilatedVcdFILE> vcdfd(new VerilatedVcdFILE(vcdfile));
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std::unique_ptr<VerilatedVcdC> tfp(new VerilatedVcdC(vcdfd.get()));
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if (vcdfile) {
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tile.trace(tfp.get(), 99); // Trace 99 levels of hierarchy
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tfp->open("");
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}
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#endif
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dtm = new dtm_t(std::vector<std::string>(argv + 1, argv + argc));
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signal(SIGTERM, handle_sigterm);
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// reset for several cycles to handle pipelined reset
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for (int i = 0; i < 10; i++) {
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tile.reset = 1;
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tile.clk = 0;
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tile.eval();
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tile.clk = 1;
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tile.eval();
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tile.reset = 0;
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}
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while (!dtm->done() && !tile.io_success && trace_count < max_cycles) {
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tile.clk = 0;
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tile.eval();
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#if VM_TRACE
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bool dump = tfp && trace_count >= start;
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if (dump)
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tfp->dump(trace_count * 2);
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#endif
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tile.clk = 1;
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tile.eval();
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#if VM_TRACE
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if (dump)
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tfp->dump(trace_count * 2 + 1);
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#endif
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trace_count++;
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}
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#if VM_TRACE
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if (tfp)
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tfp->close();
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#endif
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if (vcdfile)
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fclose(vcdfile);
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if (dtm->exit_code())
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{
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fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count);
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ret = dtm->exit_code();
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}
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else if (trace_count == max_cycles)
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{
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fprintf(stderr, "*** FAILED *** (timeout, seed %d) after %ld cycles\n", random_seed, trace_count);
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ret = 2;
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}
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else if (verbose || print_cycles)
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{
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fprintf(stderr, "Completed after %ld cycles\n", trace_count);
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}
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delete dtm;
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return ret;
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}
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