Andrew Waterman
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012da6002e
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replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
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2012-02-29 03:10:47 -08:00 |
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Andrew Waterman
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c99f6bbeb7
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separate memory request command and data
also, merge some VLSI/C++ test harness functionality
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2012-02-28 19:06:23 -08:00 |
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Yunsup Lee
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94ba32bbd3
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change package name and sbt project name to rocket
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2012-02-25 17:09:26 -08:00 |
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Andrew Waterman
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7c929afe2b
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HTIF now controls CPU reset
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2012-02-22 19:30:03 -08:00 |
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Andrew Waterman
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9a80adef50
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only instantiate VI$ if HAVE_VEC
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2012-02-21 15:53:19 -08:00 |
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Andrew Waterman
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6135615104
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unify cache backend interfaces; generify arbiter
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2012-02-20 00:51:48 -08:00 |
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Andrew Waterman
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7034c9be65
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new htif protocol and implementation
You must update your fesvr and isasim!
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2012-02-19 23:15:45 -08:00 |
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Andrew Waterman
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9af86633d7
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invalidate I$ prefetcher when invalidating I$
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2012-02-17 17:56:01 -08:00 |
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Henry Cook
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d46e59a16d
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Abstract base nbcache class
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2012-02-16 12:34:51 -08:00 |
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Yunsup Lee
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6bdf9dc513
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hwacha integration: now it compiles correctly!
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2012-02-14 23:34:57 -08:00 |
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Andrew Waterman
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1d604bcd49
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remove top-level Makefile
new, simpler build instructions are in the README.
note that for "make run-asm-tests-debug" you need to update your fesvr.
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2012-02-14 02:53:43 -08:00 |
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Andrew Waterman
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6c2d8a37ae
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remove a partial update that makes chisel barf
chisel regards it as a combinational loop, even though it isn't.
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2012-02-13 16:45:29 -08:00 |
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Andrew Waterman
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25ecfb9bbc
|
clean up caches
- remove incompatible blocking D$
- remove direct-mapped nonblocking cache
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2012-02-12 20:32:06 -08:00 |
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Andrew Waterman
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128ec567ed
|
make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
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2012-02-09 01:34:00 -08:00 |
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Andrew Waterman
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01a156eb98
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make # of dcache lines configurable
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2012-02-01 21:11:45 -08:00 |
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Henry Cook
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c5a4eaa0a1
|
Associative cache, boots kernel
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2012-02-01 13:26:04 -08:00 |
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Andrew Waterman
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97c379f1d7
|
made I$ associative
|
2012-01-24 16:51:30 -08:00 |
|
Henry Cook
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8766438bb9
|
Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
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2012-01-23 17:09:23 -08:00 |
|
Henry Cook
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7e25749581
|
Groundwork for assoc cache implementation
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2012-01-18 17:09:35 -08:00 |
|
Andrew Waterman
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07f184df2f
|
adhere to new chisel c naming convention
|
2012-01-18 15:23:21 -08:00 |
|
Andrew Waterman
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4807d7222b
|
use replay to handle I$ misses
this eliminates a long path in the fetch stage
|
2012-01-11 19:20:20 -08:00 |
|
Andrew Waterman
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8308345364
|
work in progress on hellacache
|
2011-12-10 07:01:47 -08:00 |
|
Rimas Avizienis
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e894b79870
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caches now use Mem4() memories for tag+data arrays
|
2011-12-03 19:41:15 -08:00 |
|
Rimas Avizienis
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e96430d862
|
integrating ITLB & PTW
|
2011-11-09 14:52:17 -08:00 |
|
Rimas Avizienis
|
c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
|
2011-10-25 23:02:47 -07:00 |
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