55 lines
1.4 KiB
Scala
55 lines
1.4 KiB
Scala
package Top {
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import Chisel._
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import Node._;
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import Constants._;
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class ioTop extends Bundle {
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val debug = new ioDebug();
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val console = new ioConsole();
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val host = new ioHost();
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val mem = new ioMem();
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}
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class Top() extends Component {
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val io = new ioTop();
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val cpu = new rocketProc();
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val icache = new rocketICacheDM(128, 32); // lines, address bits
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val icache_pf = new rocketIPrefetcher();
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val dcache = new rocketDCacheDM_flush(128, 32);
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val arbiter = new rocketMemArbiter();
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arbiter.io.mem ^^ io.mem;
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arbiter.io.dcache <> dcache.io.mem;
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arbiter.io.icache <> icache_pf.io.mem;
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cpu.io.host ^^ io.host;
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cpu.io.debug ^^ io.debug;
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cpu.io.console ^^ io.console;
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icache.io.mem <> icache_pf.io.icache;
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cpu.io.imem <> icache.io.cpu;
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cpu.io.dmem <> dcache.io.cpu;
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}
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object top_main {
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def main(args: Array[String]) = {
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// Can turn off --debug and --vcd when done with debugging to improve emulator performance
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// val cpu_args = args ++ Array("--target-dir", "generated-src","--debug","--vcd");
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val cpu_args = args ++ Array("--target-dir", "generated-src","--debug");
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// Set variables based off of command flags
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// for(a <- args) {
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// a match {
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// case "-bp" => isBranchPrediction = true;
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// case any =>
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// }
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// }
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chiselMain(cpu_args, () => new Top());
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}
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}
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}
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