30c0635bb3
subsystem: add some inter-wrapper buffer params
2018-02-23 15:31:18 -08:00
95294bbdcb
PatternPusher: put data at correct address when misaligned ( #1249 )
2018-02-23 15:20:56 -08:00
ad823ef43c
subsystem: pbus crossing type
2018-02-23 13:52:18 -08:00
5725e17969
subsystem: even more general coupler methods
2018-02-23 13:52:12 -08:00
87eed645d8
Fix JTAG cover description ( #1248 )
2018-02-23 12:13:31 -08:00
5b1d72c776
subsystem: expose HasTiles Parameters
2018-02-22 23:46:08 -08:00
099bbec666
subsystem: more buswrapper coupling methods
2018-02-22 23:45:21 -08:00
2e548c9ad2
Added functional covers
2018-02-22 23:20:12 -08:00
aad75f2285
Implement misa.C proposal
...
This proposal hasn't been adopted yet, but anything is better than the
current implementation, where clearing misa.C when the PC is misaligned
is effectively undefined.
2018-02-22 15:12:19 -08:00
c1ee31d133
Fix debug trigger point for stores
...
In Rocket, debug triggers are supposed to happen before a store
occurs, rather than after. Previously, we reported the exception
on the store's PC, but the store occurred anyway. This probably
hasn't been problematic in practice because most stores are
idempotent.
2018-02-22 14:56:57 -08:00
78883d13e8
subsystem: add TLIdentity.gen and make wrappers more flexible
2018-02-21 18:22:06 -08:00
eaa908d44f
subsystem: more buswrapper methods
2018-02-21 14:52:59 -08:00
e237f72539
subsystem: XSubsystemModule => XSubsystemModuleImp
2018-02-21 14:52:59 -08:00
1af02f754e
groundtest: fix filename
2018-02-21 14:52:59 -08:00
030c6f0206
subsystem: bus wrappers now in BaseSubsystem
2018-02-21 14:52:59 -08:00
b617e26c13
util: augment String and use to name couplers
2018-02-21 14:43:47 -08:00
a6d3965491
tilelink: bus wrapper scopes called 'couplers'
2018-02-21 14:43:47 -08:00
57edd7facf
subsystem: streamline toTile and fromTile attachment
2018-02-21 14:43:47 -08:00
ef3addee7b
diplomacy: put full module + instance path into graphml Description
2018-02-21 14:43:47 -08:00
62aee56807
diplomacy: base instance names on ValName and module names on className
2018-02-21 14:43:47 -08:00
3f436a7612
subsystem: new bus attachment api
2018-02-21 14:43:47 -08:00
8462ea3d5b
coreplex => subsystem
2018-02-21 14:42:24 -08:00
8998a97ea1
Preserve WithRV32 behavior: FLEN = 32
2018-02-20 18:28:47 -08:00
1dc1e2c099
support testing RV32D configs
2018-02-20 16:16:39 -08:00
d4fb7ad6a2
DefaultRV32Config should provide fdiv/fsqrt
...
This is a holdover from before we had built the functional unit.
2018-02-20 16:16:39 -08:00
b487448961
Add FPUParams.fLen option, decoupled from xLen
2018-02-20 16:16:39 -08:00
5e35015651
Minor Rocket fixes to support fLen != xLen
2018-02-20 16:16:39 -08:00
bd29184e11
debug: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
62f9b84439
plic: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
52e22a1dd8
clint: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
1bac2cbdf8
Give Rocket priority over DTIM TL port
...
The TL port can easily starve the processor, even at only 20% utilization,
because of a bad interaction with the pipeline. Giving the processor
static priority is OK in practice, since <50% of instructions are loads
and stores in typical workloads. Even if it executes 100% loads and stores,
it must eventually encounter an I$ miss, taken branch, or exception, so
even malicious code can't permanently starve the TL port.
2018-02-20 11:23:10 -08:00
5affd3bec2
RegFieldDesc: fix the output produced for undescribed registers
2018-02-16 10:24:12 -08:00
cf7cd03d64
Merge pull request #1239 from freechipsproject/reduce_debug_flags
...
Reduce Debug Module "flags"
2018-02-16 08:53:41 -08:00
d72abb7a12
Debug: revert change to how flags are named
2018-02-15 21:49:32 -08:00
dcfbdabe60
CacheCork: better document edge conditions
2018-02-15 19:14:30 -08:00
ecd069dca4
tilelink: allow FIFO caches
...
Probably not a smart thing to build, but not illegal!
2018-02-15 19:09:37 -08:00
acecc407a5
HellaCache: we do NOT really support probe below the block size!
...
If we did, you would somehow have to retain ownership of the
unprobed parts of the block, in case they happened to be dirty.
2018-02-15 19:08:43 -08:00
c34b940d9a
ElaborationArtefacts: revert unintentional change
2018-02-15 14:23:54 -08:00
e0c3b22d61
RegFieldDesc: same string used to insert/compare
2018-02-15 14:23:27 -08:00
b95f68447f
RegFieldDesc: Prevent different RegField JSONS from overwriting eachother.
2018-02-15 14:01:47 -08:00
64d3731e45
RegFieldDesc: don't put characters into names that need to be sanitized
2018-02-15 13:25:06 -08:00
197699b93a
Debug: don't need to fully populate flags array
2018-02-15 13:23:51 -08:00
fa412246b3
Error: don't be an exception wrt. caching
...
Prior to this PR, the error device was allowed to be cached by
multiple actors despite never probing any of them. This is a
pretty unusual set of properties that has caused us trouble
several times now in the past.
Let's instead put the Error device into one of two very well
established categories: a straight-up MMIO device or a tracked
memory region.
2018-02-14 23:02:55 -08:00
de91672e9a
RegFieldDesc: simplify the output RegFieldDesc JSON to just a list of reg fields
2018-02-12 08:32:52 -08:00
7bf0121f07
PLIC: correct some descriptions
2018-02-12 08:31:29 -08:00
08acbe1a29
RegFieldDesc: Clean up both descriptions and JSON presentations
2018-02-11 23:57:57 -08:00
5ab4204e8a
RegField: the JSON will just leave things out of type None
2018-02-11 22:51:36 -08:00
3b44f380d8
TLRegMapper: emit a JSON file describing the register fields
2018-02-11 22:51:36 -08:00
256f8ffc6b
Clint: Annotate regmap with RegFieldDesc
2018-02-11 21:33:09 -08:00
718c88a8f9
PLIC: Annotate regmap with RegFieldDescs
2018-02-11 21:05:17 -08:00
13b120fb01
Debug: Annotate regmaps with RegFieldDescs
2018-02-10 20:11:24 -08:00
7abf6e1c8a
RegMapper: Update cover props to use new RegFieldDesc objects
2018-02-10 13:17:38 -08:00
4ab1585a78
Register Field: Add a more verbose description object
...
Add versions of the RegField functions to take it in, and
update Example device to use it.
2018-02-10 13:17:18 -08:00
fe277cf6f0
Merge branch 'master' into auto-plusargs
2018-02-06 18:38:44 -08:00
9f6d586e8c
Add PLIC covers ( #1229 )
...
* Add another FPU hazard cover
* Add some PLIC covers
2018-02-06 17:33:33 -08:00
efc6c9cbd3
Let user of CSRFile decide when to set tval
...
I also renamed badaddr to tval (the correct name).
2018-02-06 14:05:03 -08:00
a59fc3bdaa
Teach MulDiv to do either mul-only or div-only by setting unroll=0
2018-02-06 14:03:17 -08:00
69441930b5
Rationalize ALU function encoding
...
MULHSU and MULHU should match their ISA funct3 encodings to slightly
reduce HW cost.
2018-02-06 14:00:37 -08:00
5294523551
Keep io.cpu.s1_data for visibility ( #1218 )
2018-01-31 14:31:42 -08:00
7dad486707
util: updates to internal Generator API
2018-01-30 15:19:37 -08:00
bd50a1a4bc
config: remove deprecated Parameters.root
2018-01-30 11:52:44 -08:00
46751bedeb
config: MapParameters are back in style
2018-01-30 11:52:44 -08:00
f4853c4f63
Add cover properties to Core CSRs ( #1212 )
2018-01-30 00:01:19 -08:00
b5ff853e86
Sign-extend the depc CSR ( #1209 )
2018-01-26 12:07:33 -08:00
8d8e4e1399
Merge pull request #1196 from freechipsproject/interrupt-cover
...
Cover all exceptions and interrupts
2018-01-25 18:06:13 -08:00
d2399b6d0e
Cover all exceptions and interrupts
2018-01-25 16:14:56 -08:00
a749326deb
Add cover points to registers ( #1208 )
2018-01-24 21:37:24 -08:00
7a0252fdfc
Add some covers for FPU structural hazards
2018-01-23 16:32:03 -08:00
a2ca82f92c
Add VM covers
2018-01-23 16:13:35 -08:00
c32150b994
ResetCatchAndSync: work also in the context of a RawModule ( #1202 )
2018-01-19 19:45:52 -08:00
f6f5606f8e
diplomacy: run user instantiate() method after nodes are initialized ( #1198 )
2018-01-18 14:57:47 -08:00
5cc1411e14
Merge pull request #1199 from freechipsproject/require-messages
...
rocket: add address to tlb permissions require msgs
2018-01-18 14:53:25 -08:00
bf5dd6dac3
Replace Parameters in cover with globally setable implementation ( #1200 )
...
This change is made in anticipation of a proper coverage library
2018-01-18 14:45:36 -08:00
24c1235500
rocket: add address to tlb permissions require msgs
2018-01-18 10:31:51 -08:00
5854fb5f7c
SourceShrinker improvements ( #1197 )
...
* SourceShrinker: preserve FIFO guarantees of slaves
* tilelink: document that Releases can use TtoT, BtoB, and NtoN
TtoT is needed for write-through caches.
2018-01-17 18:02:19 -08:00
338e453a91
JTAG: Use new withClock way of overriding clocks ( #1072 )
...
* JTAG: Use new withClock way of overriding clocks
the override clock way is deprecated
* JTAG: use withClock instead of override clock
* JTAG: extend Module for ClockedCounter
* JTAG: Don't use deprecated clock constructs
* JTAG: Remove another override_clock
* Rename "NegativeEdgeLatch"
because it's not a latch, it's just a register on the negative edge of the clock.
* Use the appropriately named NegEdgeReg
* JTAG: Rename another NegativeEdgeLatch
2018-01-17 13:59:05 -08:00
355d3b15e8
Merge 'origin/master' into auto-plusargs
2018-01-16 15:45:53 -05:00
80ca018e3a
Add cover points for BusErrorUnit ( #1193 )
2018-01-15 18:00:29 -08:00
04af785a5f
Emit plusArgs for unit tests
...
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 17:54:40 -05:00
09c1d034fa
Explicitly name PlusArg serializers as *_cHeader
...
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 17:00:12 -05:00
cfd49f87c1
Use longname for ElaborationArtefact emission
...
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 16:55:13 -05:00
e52d52ae99
Link PlusArg to emulator command line options
...
- adds a mutable singleton (PlusArgArtefacts) to store information
about Rocket PlusArgs
- adds methods to PlusArgArtefacts to emit C snippets that are
consumed by emulator.cc for correct argument parsing and help text
generation
- emits snippets in $(CONFIG).plusArgs via BaseCoreplex-set
ElaborationArtefacts
- modify emulator/Makefrag-verilator to include $(CONFIG).plusArgs
- cleanup help text (docstring) for existing PlusArgs
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 14:32:55 -05:00
5fe0bb0d6a
Merge remote-tracking branch 'origin/master' into refactored_rbb
2018-01-09 21:34:14 -08:00
f5211765e9
Merge pull request #1177 from freechipsproject/dont-touch-2
...
Make more use of chisel3.experimental.DontTouch
2018-01-09 15:13:55 -08:00
c152962642
Dual-port RAM replaced with single-port RAM for tag_array in HellaCache ( #1181 )
...
In accordance with https://github.com/freechipsproject/chisel3/issues/752
2018-01-09 13:06:43 -08:00
15c54b1c5a
tile: intSinkNode belongs in HasExternalInterrupts
2018-01-08 19:38:10 -08:00
11e5b620f8
tile: disable more monitors on slave port
2018-01-08 18:42:25 -08:00
5075a93e6c
util: dontTouch work-around for zero width aggregates
2018-01-08 15:58:28 -08:00
7fc8337cdb
Merge pull request #1180 from freechipsproject/addrwregdesc
...
Allow rwReg to pass name and description to RegField for documentation.
2018-01-08 09:44:44 -08:00
a530646d15
Merge remote-tracking branch 'origin/master' into refactored_rbb
2018-01-08 09:11:27 -08:00
4fd4ae38e3
Merge pull request #1176 from freechipsproject/fix-tl-port
...
Fix TL MMIO port
2018-01-05 20:37:44 -08:00
e6661a6982
Debug regressions: use a plusarg to enable remote bitbang.
2018-01-05 17:08:21 -08:00
8425086f98
Allow rwReg to pass name and description to RegField for documentation.
2018-01-05 16:59:58 -08:00
4449dd0baa
Debug regressions: Add necessary config scripts
2018-01-05 16:03:59 -08:00
e82328336e
Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
...
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
b77b93b0b4
util: dontTouchPortsExcept
2018-01-05 14:06:00 -08:00
000cde2f8a
Make ErrorDevice UNCACHEABLE instead of UNCACHED
...
...even though it still supports Acquire. This avoids needing to flush
the D$ on FENCE.I because of the presence of the ErrorDevice.
2018-01-05 14:00:42 -08:00
ad0b9a0b1b
Reduce cases in which FENCE.I must flush D$
...
Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.
2018-01-05 13:58:14 -08:00
4853d1355f
rocket: dontTouch HellaCache.io.cpu.resp
2018-01-05 12:50:24 -08:00
847efde385
coreplex: dontTouch the tile_inputs wire
2018-01-05 12:47:41 -08:00
Henry Cook
Wesley W. Terpstra
Jacob Chang
Bipul Talukdar
Andrew Waterman
Megan Wachs
Andrew Waterman
solomatnikov
Jack Koenig
Schuyler Eldridge
pentin-as
Albert Huntington