2014-09-13 03:06:41 +02:00
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// See LICENSE for license details.
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2012-03-25 00:56:59 +01:00
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package rocket
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import Chisel._
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2012-10-02 01:08:41 +02:00
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import uncore._
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2012-11-18 02:24:08 +01:00
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import Util._
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2015-10-22 03:18:32 +02:00
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import cde.{Parameters, Field}
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2012-03-25 00:56:59 +01:00
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2014-09-08 02:54:41 +02:00
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case object CoreName extends Field[String]
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2015-12-02 02:54:56 +01:00
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case object BuildRoCC extends Field[Seq[RoccParameters]]
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case class RoccParameters(
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opcodes: OpcodeSet,
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generator: Parameters => RoCC,
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2015-12-03 01:28:23 +01:00
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nMemChannels: Int = 0,
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2016-02-25 07:39:00 +01:00
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nPTWPorts : Int = 0,
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2016-01-14 20:37:58 +01:00
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csrs: Seq[Int] = Nil,
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useFPU: Boolean = false)
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2014-08-08 21:23:02 +02:00
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2015-10-06 06:48:05 +02:00
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abstract class Tile(resetSignal: Bool = null)
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(implicit p: Parameters) extends Module(_reset = resetSignal) {
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2015-11-26 01:02:27 +01:00
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val buildRocc = p(BuildRoCC)
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val usingRocc = !buildRocc.isEmpty
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val nRocc = buildRocc.size
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2015-12-02 03:14:58 +01:00
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val nFPUPorts = buildRocc.filter(_.useFPU).size
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2015-11-26 01:02:27 +01:00
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val nDCachePorts = 2 + nRocc
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2016-02-25 07:39:00 +01:00
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val nPTWPorts = 2 + p(RoccNPTWPorts)
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2015-10-21 00:02:24 +02:00
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val nCachedTileLinkPorts = 1
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2015-11-26 01:02:27 +01:00
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val nUncachedTileLinkPorts = 1 + p(RoccNMemChannels)
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2015-10-21 00:02:24 +02:00
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val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
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2012-03-25 00:56:59 +01:00
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val io = new Bundle {
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2015-10-21 00:02:24 +02:00
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val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
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val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
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2015-10-06 06:48:05 +02:00
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val host = new HtifIO
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2015-11-18 03:14:30 +01:00
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val dma = new DmaIO
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2012-03-25 00:56:59 +01:00
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}
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2014-09-24 22:04:20 +02:00
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}
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2015-10-06 06:48:05 +02:00
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class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(resetSignal)(p) {
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2015-10-21 00:02:24 +02:00
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val core = Module(new Rocket()(p.alterPartial({ case CoreName => "Rocket" })))
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2015-10-06 06:48:05 +02:00
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val icache = Module(new Frontend()(p.alterPartial({
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2015-10-21 00:02:24 +02:00
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case CacheName => "L1I"
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case CoreName => "Rocket" })))
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2015-10-06 06:48:05 +02:00
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val dcache = Module(new HellaCache()(dcacheParams))
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2015-10-21 00:02:24 +02:00
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val ptw = Module(new PTW(nPTWPorts)(dcacheParams))
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2014-08-08 21:23:02 +02:00
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2015-04-11 11:26:33 +02:00
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dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
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2015-10-21 00:02:24 +02:00
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val dcArb = Module(new HellaCacheArbiter(nDCachePorts)(dcacheParams))
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2014-08-08 21:23:02 +02:00
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dcArb.io.requestor(0) <> ptw.io.mem
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dcArb.io.requestor(1) <> core.io.dmem
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2015-08-02 06:11:25 +02:00
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dcache.io.cpu <> dcArb.io.mem
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2012-03-25 00:56:59 +01:00
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2015-03-04 01:40:39 +01:00
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ptw.io.requestor(0) <> icache.io.ptw
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ptw.io.requestor(1) <> dcache.io.ptw
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2013-09-13 07:34:38 +02:00
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2015-08-02 06:11:25 +02:00
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io.host <> core.io.host
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icache.io.cpu <> core.io.imem
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2013-09-15 07:34:53 +02:00
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core.io.ptw <> ptw.io.dpath
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2015-12-01 19:22:31 +01:00
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val fpuOpt = if (p(UseFPU)) Some(Module(new FPU)) else None
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fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
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2015-07-22 02:10:56 +02:00
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2015-10-21 00:02:24 +02:00
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// Connect the caches and ROCC to the outer memory system
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io.cached.head <> dcache.io.mem
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// If so specified, build an RoCC module and wire it to core + TileLink ports,
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// otherwise just hookup the icache
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2015-11-26 01:02:27 +01:00
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io.uncached <> (if (usingRocc) {
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2015-12-03 01:28:23 +01:00
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val uncachedArb = Module(new ClientTileLinkIOArbiter(1 + nRocc))
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uncachedArb.io.in(0) <> icache.io.mem
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2015-11-26 01:02:27 +01:00
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val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
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core.io.rocc.resp <> respArb.io.out
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2015-12-02 02:54:56 +01:00
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val roccOpcodes = buildRocc.map(_.opcodes)
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2015-11-26 01:02:27 +01:00
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val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
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cmdRouter.io.in <> core.io.rocc.cmd
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2015-12-02 03:14:58 +01:00
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val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
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2016-01-14 20:37:58 +01:00
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val rocc = accelParams.generator(p.alterPartial({
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case RoccNMemChannels => accelParams.nMemChannels
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2016-02-25 07:39:00 +01:00
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case RoccNPTWPorts => accelParams.nPTWPorts
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2016-01-14 20:37:58 +01:00
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case RoccNCSRs => accelParams.csrs.size
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}))
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val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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rocc.io.cmd <> cmdRouter.io.out(i)
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2016-03-03 08:29:58 +01:00
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rocc.io.status := core.io.rocc.status
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2015-12-02 03:14:58 +01:00
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rocc.io.exception := core.io.rocc.exception
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2016-01-14 20:37:58 +01:00
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rocc.io.host_id := io.host.id
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2015-12-02 03:14:58 +01:00
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dcIF.io.requestor <> rocc.io.mem
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dcArb.io.requestor(2 + i) <> dcIF.io.cache
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2015-12-03 01:28:23 +01:00
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uncachedArb.io.in(1 + i) <> rocc.io.autl
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2015-12-02 03:14:58 +01:00
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rocc
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2015-11-26 01:02:27 +01:00
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}
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2015-12-02 01:48:05 +01:00
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if (nFPUPorts > 0) {
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fpuOpt.foreach { fpu =>
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val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts))
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2015-12-02 03:14:58 +01:00
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val fp_roccs = roccs.zip(buildRocc)
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.filter { case (_, params) => params.useFPU }
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.map { case (rocc, _) => rocc.io }
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fpArb.io.in_req <> fp_roccs.map(_.fpu_req)
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2015-12-02 01:48:05 +01:00
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fp_roccs.zip(fpArb.io.in_resp).foreach {
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2015-12-02 03:14:58 +01:00
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case (rocc, fpu_resp) => rocc.fpu_resp <> fpu_resp
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2015-12-02 01:48:05 +01:00
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}
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fpu.io.cp_req <> fpArb.io.out_req
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fpArb.io.out_resp <> fpu.io.cp_resp
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2015-12-01 19:22:31 +01:00
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}
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2015-12-02 01:48:05 +01:00
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}
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2015-12-01 19:22:31 +01:00
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2016-02-25 07:39:00 +01:00
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ptw.io.requestor.drop(2) <> roccs.flatMap(_.io.ptw)
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2015-11-26 01:02:27 +01:00
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core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
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core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
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respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
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2016-01-14 20:37:58 +01:00
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if (p(RoccNCSRs) > 0) {
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core.io.rocc.csr.rdata <> roccs.map(_.io.csr.rdata).reduce(_ ++ _)
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for ((rocc, accelParams) <- roccs.zip(buildRocc)) {
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rocc.io.csr.waddr := core.io.rocc.csr.waddr
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rocc.io.csr.wdata := core.io.rocc.csr.wdata
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rocc.io.csr.wen := core.io.rocc.csr.wen &&
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accelParams.csrs
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.map(core.io.rocc.csr.waddr === UInt(_))
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.reduce((a, b) => a || b)
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}
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}
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2015-12-03 01:28:23 +01:00
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roccs.flatMap(_.io.utl) :+ uncachedArb.io.out
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2015-11-26 01:02:27 +01:00
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} else { Seq(icache.io.mem) })
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2015-12-02 05:41:58 +01:00
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if (!usingRocc || nFPUPorts == 0) {
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fpuOpt.foreach { fpu =>
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fpu.io.cp_req.valid := Bool(false)
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fpu.io.cp_resp.ready := Bool(false)
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}
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}
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2012-03-25 00:56:59 +01:00
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}
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