2012-02-26 02:09:26 +01:00
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package rocket
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2011-10-26 08:02:47 +02:00
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2012-10-08 05:15:54 +02:00
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import Chisel._
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2016-06-28 22:15:39 +02:00
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import uncore.agents._
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import uncore.tilelink._
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import uncore.util._
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2012-10-12 01:54:28 +02:00
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import Util._
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2015-10-22 03:18:32 +02:00
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import cde.{Parameters, Field}
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2011-10-26 08:02:47 +02:00
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2015-12-03 02:17:49 +01:00
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case object ICacheBufferWays extends Field[Boolean]
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2015-10-06 06:48:05 +02:00
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trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
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2015-10-14 08:42:53 +02:00
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val outerDataBeats = p(TLKey(p(TLId))).dataBeats
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val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
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2015-03-01 02:00:05 +01:00
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val refillCyclesPerBeat = outerDataBits/rowBits
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2014-12-17 23:28:05 +01:00
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val refillCycles = refillCyclesPerBeat*outerDataBeats
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2014-09-01 22:28:58 +02:00
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}
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2014-08-12 03:36:23 +02:00
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2016-05-24 02:51:08 +02:00
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class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1CacheParameters {
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val addr = UInt(width = vaddrBits)
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2013-08-12 19:39:11 +02:00
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}
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2015-10-06 06:48:05 +02:00
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class ICacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasL1CacheParameters {
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2014-09-01 22:28:58 +02:00
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val data = Bits(width = coreInstBits)
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2014-08-12 03:36:23 +02:00
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val datablock = Bits(width = rowBits)
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2013-08-12 19:39:11 +02:00
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}
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2015-10-06 06:48:05 +02:00
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class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CacheParameters {
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2012-10-10 06:35:03 +02:00
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val io = new Bundle {
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2013-08-12 19:39:11 +02:00
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val req = Valid(new ICacheReq).flip
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2016-04-02 04:30:39 +02:00
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val s1_ppn = UInt(INPUT, ppnBits) // delayed one cycle w.r.t. req
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val s1_kill = Bool(INPUT) // delayed one cycle w.r.t. req
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2016-07-09 10:08:52 +02:00
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val s2_kill = Bool(INPUT) // delayed two cycles; prevents I$ miss emission
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2016-04-02 04:30:39 +02:00
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2013-08-12 19:39:11 +02:00
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val resp = Decoupled(new ICacheResp)
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2012-11-16 10:55:45 +01:00
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val invalidate = Bool(INPUT)
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2015-04-18 01:56:53 +02:00
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val mem = new ClientUncachedTileLinkIO
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2012-01-25 00:13:49 +01:00
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}
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2014-08-08 21:23:02 +02:00
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require(isPow2(nSets) && isPow2(nWays))
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2014-09-01 22:28:58 +02:00
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require(isPow2(coreInstBytes))
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2016-05-24 02:51:08 +02:00
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require(!usingVM || pgIdxBits >= untagBits)
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2012-01-25 00:13:49 +01:00
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2013-09-10 19:51:35 +02:00
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val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(UInt(), 4)
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2013-08-16 00:28:15 +02:00
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val state = Reg(init=s_ready)
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2013-08-12 19:39:11 +02:00
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val invalidated = Reg(Bool())
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2012-10-10 06:35:03 +02:00
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val stall = !io.resp.ready
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2015-07-16 05:24:18 +02:00
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val rdy = Wire(Bool())
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2012-10-10 06:35:03 +02:00
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2015-04-22 20:26:03 +02:00
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val refill_addr = Reg(UInt(width = paddrBits))
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2016-01-12 21:42:57 +01:00
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val s1_any_tag_hit = Wire(Bool())
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2011-10-26 08:02:47 +02:00
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2013-08-16 00:28:15 +02:00
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val s1_valid = Reg(init=Bool(false))
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2016-05-24 02:51:08 +02:00
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val s1_vaddr = Reg(UInt())
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val s1_paddr = Cat(io.s1_ppn, s1_vaddr(pgIdxBits-1,0)).toUInt
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val s1_tag = s1_paddr(tagBits+untagBits-1,untagBits)
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2012-10-10 06:35:03 +02:00
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2012-11-16 10:55:45 +01:00
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val s0_valid = io.req.valid || s1_valid && stall
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2016-05-24 02:51:08 +02:00
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val s0_vaddr = Mux(s1_valid && stall, s1_vaddr, io.req.bits.addr)
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2012-10-10 06:35:03 +02:00
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2016-04-02 04:30:39 +02:00
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s1_valid := io.req.valid && rdy || s1_valid && stall && !io.s1_kill
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2012-10-10 06:35:03 +02:00
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when (io.req.valid && rdy) {
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2016-05-24 02:51:08 +02:00
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s1_vaddr := io.req.bits.addr
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2011-11-05 04:52:21 +01:00
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}
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2012-10-10 06:35:03 +02:00
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2016-04-02 04:30:39 +02:00
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val out_valid = s1_valid && !io.s1_kill && state === s_ready
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2016-05-24 02:51:08 +02:00
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val s1_idx = s1_vaddr(untagBits-1,blockOffBits)
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2015-04-22 20:26:03 +02:00
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val s1_hit = out_valid && s1_any_tag_hit
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val s1_miss = out_valid && !s1_any_tag_hit
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rdy := state === s_ready && !s1_miss
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2012-10-10 06:35:03 +02:00
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2016-07-09 10:08:52 +02:00
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when (s1_miss && state === s_ready) {
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2016-05-24 02:51:08 +02:00
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refill_addr := s1_paddr
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2015-04-22 20:26:03 +02:00
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}
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val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
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2012-10-10 06:35:03 +02:00
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2015-03-27 07:26:03 +01:00
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val narrow_grant = FlowThroughSerializer(io.mem.grant, refillCyclesPerBeat)
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val (refill_cnt, refill_wrap) = Counter(narrow_grant.fire(), refillCycles) //TODO Zero width wire
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2014-12-07 12:09:54 +01:00
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val refill_done = state === s_refill && refill_wrap
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2015-03-27 07:26:03 +01:00
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narrow_grant.ready := Bool(true)
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2012-10-10 06:35:03 +02:00
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2015-04-22 20:26:03 +02:00
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val repl_way = if (isDM) UInt(0) else LFSR16(s1_miss)(log2Up(nWays)-1,0)
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2014-08-12 03:36:23 +02:00
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val entagbits = code.width(tagBits)
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2016-01-12 21:42:57 +01:00
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val tag_array = SeqMem(nSets, Vec(nWays, Bits(width = entagbits)))
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2016-05-24 02:51:08 +02:00
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val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
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2012-10-10 06:35:03 +02:00
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when (refill_done) {
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2015-04-22 20:26:03 +02:00
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val tag = code.encode(refill_tag).toUInt
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2015-10-18 22:09:17 +02:00
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tag_array.write(s1_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
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2012-11-05 01:39:25 +01:00
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}
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2012-07-12 23:50:12 +02:00
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2014-08-08 21:23:02 +02:00
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val vb_array = Reg(init=Bits(0, nSets*nWays))
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2012-10-10 06:35:03 +02:00
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when (refill_done && !invalidated) {
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2015-04-22 20:26:03 +02:00
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vb_array := vb_array.bitSet(Cat(repl_way, s1_idx), Bool(true))
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2012-10-10 06:35:03 +02:00
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}
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2012-11-16 10:55:45 +01:00
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when (io.invalidate) {
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2012-07-12 23:50:12 +02:00
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vb_array := Bits(0)
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2012-10-10 06:35:03 +02:00
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invalidated := Bool(true)
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2012-07-12 23:50:12 +02:00
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}
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2016-01-12 21:42:57 +01:00
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val s1_disparity = Wire(Vec(nWays, Bool()))
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2014-08-08 21:23:02 +02:00
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for (i <- 0 until nWays)
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2015-04-22 20:26:03 +02:00
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when (s1_valid && s1_disparity(i)) { vb_array := vb_array.bitSet(Cat(UInt(i), s1_idx), Bool(false)) }
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2012-10-10 06:35:03 +02:00
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2016-01-12 21:42:57 +01:00
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val s1_tag_match = Wire(Vec(nWays, Bool()))
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val s1_tag_hit = Wire(Vec(nWays, Bool()))
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val s1_dout = Wire(Vec(nWays, Bits(width = rowBits)))
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2012-11-25 07:00:43 +01:00
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2014-08-08 21:23:02 +02:00
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for (i <- 0 until nWays) {
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2016-05-24 02:51:08 +02:00
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val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_vaddr(untagBits-1,blockOffBits))).toBool
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2015-09-12 00:43:07 +02:00
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val tag_out = tag_rdata(i)
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2015-04-22 20:26:03 +02:00
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val s1_tag_disparity = code.decode(tag_out).error
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2014-08-12 03:36:23 +02:00
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s1_tag_match(i) := tag_out(tagBits-1,0) === s1_tag
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2015-04-22 20:26:03 +02:00
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s1_tag_hit(i) := s1_vb && s1_tag_match(i)
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s1_disparity(i) := s1_vb && (s1_tag_disparity || code.decode(s1_dout(i)).error)
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2012-10-10 06:35:03 +02:00
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}
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2015-04-22 20:26:03 +02:00
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s1_any_tag_hit := s1_tag_hit.reduceLeft(_||_) && !s1_disparity.reduceLeft(_||_)
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2012-10-10 06:35:03 +02:00
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2014-08-08 21:23:02 +02:00
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for (i <- 0 until nWays) {
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2016-01-12 21:42:57 +01:00
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val data_array = SeqMem(nSets * refillCycles, Bits(width = code.width(rowBits)))
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2015-07-11 22:32:45 +02:00
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val wen = narrow_grant.valid && repl_way === UInt(i)
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when (wen) {
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val e_d = code.encode(narrow_grant.bits.data).toUInt
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2015-08-06 17:03:10 +02:00
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if(refillCycles > 1) data_array.write(Cat(s1_idx, refill_cnt), e_d)
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else data_array.write(s1_idx, e_d)
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2012-10-10 06:35:03 +02:00
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}
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2016-05-24 02:51:08 +02:00
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val s0_raddr = s0_vaddr(untagBits-1,blockOffBits-(if(refillCycles > 1) refill_cnt.getWidth else 0))
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2016-01-28 20:44:59 +01:00
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s1_dout(i) := data_array.read(s0_raddr, !wen && s0_valid)
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2012-01-25 01:51:30 +01:00
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}
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2011-12-04 04:41:15 +01:00
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2011-11-07 09:58:25 +01:00
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// output signals
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2015-12-03 02:17:49 +01:00
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if (p(ICacheBufferWays)) {
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val s2_hit = RegEnable(s1_hit, !stall)
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val s2_tag_hit = RegEnable(s1_tag_hit, !stall)
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val s2_dout = RegEnable(s1_dout, !stall)
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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io.resp.valid := s2_hit
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} else {
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io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout)
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io.resp.valid := s1_hit
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}
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2016-07-09 10:08:52 +02:00
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io.mem.acquire.valid := state === s_request && !io.s2_kill
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2015-10-18 22:09:17 +02:00
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io.mem.acquire.bits := GetBlock(addr_block = refill_addr >> blockOffBits)
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2011-10-26 08:02:47 +02:00
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// control state machine
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switch (state) {
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is (s_ready) {
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2015-04-22 20:26:03 +02:00
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when (s1_miss) { state := s_request }
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2012-03-06 09:31:44 +01:00
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invalidated := Bool(false)
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2011-10-26 08:02:47 +02:00
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}
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2012-10-10 06:35:03 +02:00
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is (s_request) {
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2015-03-27 07:26:03 +01:00
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when (io.mem.acquire.ready) { state := s_refill_wait }
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2016-07-09 10:08:52 +02:00
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when (io.s2_kill) { state := s_ready }
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2011-10-26 08:02:47 +02:00
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}
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is (s_refill_wait) {
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2013-01-22 02:18:23 +01:00
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when (io.mem.grant.valid) { state := s_refill }
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2011-10-26 08:02:47 +02:00
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}
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is (s_refill) {
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2012-10-10 06:35:03 +02:00
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when (refill_done) { state := s_ready }
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2011-10-26 08:02:47 +02:00
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}
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2012-10-10 06:35:03 +02:00
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}
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2011-10-26 08:02:47 +02:00
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}
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