2014-09-13 00:31:38 +02:00
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// See LICENSE for license details.
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2012-09-27 21:59:45 +02:00
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package uncore
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2012-04-03 21:03:05 +02:00
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import Chisel._
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2014-08-08 21:21:57 +02:00
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case object NReleaseTransactors extends Field[Int]
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case object NAcquireTransactors extends Field[Int]
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2014-11-12 21:55:07 +01:00
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case object L2StoreDataQueueDepth extends Field[Int]
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2014-08-08 21:21:57 +02:00
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case object NClients extends Field[Int]
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2014-04-27 04:11:36 +02:00
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2014-08-12 03:35:49 +02:00
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abstract trait CoherenceAgentParameters extends UsesParameters {
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2014-08-08 21:21:57 +02:00
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val co = params(TLCoherence)
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2014-11-12 21:55:07 +01:00
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val nReleaseTransactors = 1
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2014-08-12 03:35:49 +02:00
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val nAcquireTransactors = params(NAcquireTransactors)
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val nTransactors = nReleaseTransactors + nAcquireTransactors
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val nClients = params(NClients)
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2014-11-12 21:55:07 +01:00
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val sdqDepth = params(L2StoreDataQueueDepth)
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val sdqIdBits = math.max(log2Up(nReleaseTransactors) + 1, log2Up(params(L2StoreDataQueueDepth))) + 1
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2014-08-12 03:35:49 +02:00
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}
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2014-09-24 20:14:36 +02:00
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abstract class CoherenceAgent(innerId: String, outerId: String) extends Module
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2014-08-12 03:35:49 +02:00
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with CoherenceAgentParameters {
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2013-01-17 08:57:35 +01:00
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val io = new Bundle {
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2014-09-24 20:14:36 +02:00
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val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
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val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
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2014-08-12 03:35:49 +02:00
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val incoherent = Vec.fill(nClients){Bool()}.asInput
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2013-01-17 08:57:35 +01:00
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}
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}
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2014-09-24 20:14:36 +02:00
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class L2CoherenceAgent(bankId: Int, innerId: String, outerId: String) extends
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CoherenceAgent(innerId, outerId) {
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2013-08-02 23:55:06 +02:00
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2014-11-12 21:55:07 +01:00
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// Queue to store impending UncachedWrite data
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val sdq_val = Reg(init=Bits(0, sdqDepth))
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val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0))
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val sdq_rdy = !sdq_val.andR
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val sdq_enq = io.inner.acquire.valid && io.inner.acquire.ready && co.messageHasData(io.inner.acquire.bits.payload)
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val sdq = Vec.fill(sdqDepth){Reg(io.inner.acquire.bits.payload.data)}
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when (sdq_enq) { sdq(sdq_alloc_id) := io.inner.acquire.bits.payload.data }
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2013-08-02 23:55:06 +02:00
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// Create SHRs for outstanding transactions
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2014-08-12 03:35:49 +02:00
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val trackerList = (0 until nReleaseTransactors).map(id =>
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2014-11-12 21:55:07 +01:00
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Module(new VoluntaryReleaseTracker(id, bankId, innerId, outerId), {case TLDataBits => sdqIdBits})) ++
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2014-08-12 03:35:49 +02:00
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(nReleaseTransactors until nTransactors).map(id =>
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2014-11-12 21:55:07 +01:00
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Module(new AcquireTracker(id, bankId, innerId, outerId), {case TLDataBits => sdqIdBits}))
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2013-01-17 08:57:35 +01:00
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2013-08-02 23:55:06 +02:00
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// Propagate incoherence flags
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2013-03-20 22:10:16 +01:00
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trackerList.map(_.io.tile_incoherent := io.incoherent.toBits)
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2013-01-17 08:57:35 +01:00
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2013-03-26 00:20:12 +01:00
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// Handle acquire transaction initiation
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2014-04-30 01:49:18 +02:00
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val acquire = io.inner.acquire
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2013-01-29 01:39:45 +01:00
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val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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2013-04-10 22:46:31 +02:00
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val block_acquires = any_acquire_conflict
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2013-01-17 08:57:35 +01:00
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2013-08-12 19:36:44 +02:00
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val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
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2013-03-20 22:10:16 +01:00
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for( i <- 0 until trackerList.size ) {
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2014-04-30 01:49:18 +02:00
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val t = trackerList(i).io.inner
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2014-03-29 18:53:49 +01:00
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alloc_arb.io.in(i).valid := t.acquire.ready
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t.acquire.bits := acquire.bits
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2014-11-12 21:55:07 +01:00
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t.acquire.bits.payload.data := Cat(sdq_alloc_id, UInt(1))
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2014-03-29 18:53:49 +01:00
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t.acquire.valid := alloc_arb.io.in(i).ready
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2013-01-17 08:57:35 +01:00
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}
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2014-11-12 21:55:07 +01:00
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acquire.ready := trackerList.map(_.io.inner.acquire.ready).reduce(_||_) && sdq_rdy && !block_acquires
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alloc_arb.io.out.ready := acquire.valid && sdq_rdy && !block_acquires
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2013-01-17 08:57:35 +01:00
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// Handle probe request generation
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2013-09-11 01:15:41 +02:00
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val probe_arb = Module(new Arbiter(new LogicalNetworkIO(new Probe), trackerList.size))
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2014-04-30 01:49:18 +02:00
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io.inner.probe <> probe_arb.io.out
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probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.probe }
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2013-01-17 08:57:35 +01:00
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2013-04-09 23:09:36 +02:00
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// Handle releases, which might be voluntary and might have data
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2014-04-30 01:49:18 +02:00
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val release = io.inner.release
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2014-03-29 18:53:49 +01:00
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val voluntary = co.isVoluntary(release.bits.payload)
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2013-01-29 01:39:45 +01:00
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val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
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2013-04-10 22:46:31 +02:00
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val block_releases = Bool(false)
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2013-08-12 19:36:44 +02:00
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val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
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2014-11-05 23:21:38 +01:00
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val release_idx = Mux(voluntary, UInt(0), conflict_idx)
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// TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
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2013-03-20 22:10:16 +01:00
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for( i <- 0 until trackerList.size ) {
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2014-04-30 01:49:18 +02:00
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val t = trackerList(i).io.inner
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2014-03-29 18:53:49 +01:00
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t.release.bits := release.bits
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2014-11-12 21:55:07 +01:00
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t.release.bits.payload.data := (if (i < nReleaseTransactors) Cat(UInt(i), UInt(2)) else UInt(0))
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2014-03-29 18:53:49 +01:00
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t.release.valid := release.valid && (release_idx === UInt(i)) && !block_releases
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2013-01-17 08:57:35 +01:00
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}
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2014-04-30 01:49:18 +02:00
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release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx) && !block_releases
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2013-01-17 08:57:35 +01:00
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2014-11-12 21:55:07 +01:00
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val vwbdq = Vec.fill(nReleaseTransactors){ Reg(release.bits.payload.data) }
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when(voluntary && release.fire()) {
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vwbdq(release_idx) := release.bits.payload.data
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}
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2013-01-17 08:57:35 +01:00
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// Reply to initial requestor
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2013-09-11 01:15:41 +02:00
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val grant_arb = Module(new Arbiter(new LogicalNetworkIO(new Grant), trackerList.size))
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2014-11-12 21:55:07 +01:00
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io.inner.grant.bits.payload.data := io.outer.grant.bits.payload.data
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2014-04-30 01:49:18 +02:00
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io.inner.grant <> grant_arb.io.out
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grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.grant }
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2013-01-17 08:57:35 +01:00
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// Free finished transactions
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2014-04-30 01:49:18 +02:00
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val ack = io.inner.finish
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trackerList.map(_.io.inner.finish.valid := ack.valid)
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trackerList.map(_.io.inner.finish.bits := ack.bits)
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2013-01-23 05:09:21 +01:00
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ack.ready := Bool(true)
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2013-01-17 08:57:35 +01:00
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// Create an arbiter for the one memory port
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2014-09-24 20:14:36 +02:00
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val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size),
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2014-11-12 21:55:07 +01:00
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{ case TLId => outerId; case TLDataBits => sdqIdBits })
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2014-04-30 01:49:18 +02:00
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outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.outer }
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2014-11-12 21:55:07 +01:00
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val is_in_sdq = outer_arb.io.out.acquire.bits.payload.data(0)
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val is_in_vwbdq = outer_arb.io.out.acquire.bits.payload.data(1)
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val free_sdq_id = outer_arb.io.out.acquire.bits.payload.data >> UInt(1)
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val free_vwbdq_id = outer_arb.io.out.acquire.bits.payload.data >> UInt(2)
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val free_sdq = io.outer.acquire.fire() && co.messageHasData(io.outer.acquire.bits.payload) && is_in_sdq
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io.outer.acquire.bits.payload.data := Mux(is_in_sdq, sdq(free_sdq_id),
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Mux(is_in_vwbdq, vwbdq(free_vwbdq_id), release.bits.payload.data))
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2014-04-30 01:49:18 +02:00
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io.outer <> outer_arb.io.out
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2014-11-12 21:55:07 +01:00
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// Update SDQ valid bits
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when (io.outer.acquire.valid || sdq_enq) {
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sdq_val := sdq_val & ~(UIntToOH(free_sdq_id) & Fill(sdqDepth, free_sdq)) |
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PriorityEncoderOH(~sdq_val(sdqDepth-1,0)) & Fill(sdqDepth, sdq_enq)
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}
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2013-01-17 08:57:35 +01:00
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}
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2013-01-29 01:39:45 +01:00
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2014-09-24 20:14:36 +02:00
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abstract class XactTracker(innerId: String, outerId: String) extends Module {
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2014-08-08 21:21:57 +02:00
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val (co, nClients) = (params(TLCoherence),params(NClients))
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2013-01-17 08:57:35 +01:00
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val io = new Bundle {
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2014-09-24 20:14:36 +02:00
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val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
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val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
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2014-08-08 21:21:57 +02:00
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val tile_incoherent = Bits(INPUT, params(NClients))
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2013-03-20 22:10:16 +01:00
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val has_acquire_conflict = Bool(OUTPUT)
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val has_release_conflict = Bool(OUTPUT)
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2013-01-29 01:39:45 +01:00
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}
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2014-03-29 18:53:49 +01:00
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2014-04-30 01:49:18 +02:00
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val c_acq = io.inner.acquire.bits
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val c_rel = io.inner.release.bits
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val c_gnt = io.inner.grant.bits
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val c_ack = io.inner.finish.bits
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val m_gnt = io.outer.grant.bits
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2013-01-29 01:39:45 +01:00
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}
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2014-09-24 20:14:36 +02:00
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class VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends XactTracker(innerId, outerId) {
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2013-09-10 19:54:51 +02:00
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val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(UInt(), 4)
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2013-08-16 00:27:38 +02:00
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val state = Reg(init=s_idle)
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2013-01-29 01:39:45 +01:00
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val xact = Reg{ new Release }
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2014-08-08 21:21:57 +02:00
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val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
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2013-01-29 01:39:45 +01:00
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io.has_acquire_conflict := Bool(false)
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2014-11-12 21:55:07 +01:00
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) &&
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2014-03-29 18:53:49 +01:00
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(state != s_idle)
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2013-03-20 22:10:16 +01:00
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2014-04-30 01:49:18 +02:00
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io.outer.grant.ready := Bool(false)
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io.outer.acquire.valid := Bool(false)
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io.outer.acquire.bits.header.src := UInt(bankId)
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//io.outer.acquire.bits.header.dst TODO
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2014-11-12 02:36:55 +01:00
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io.outer.acquire.bits.payload := Bundle(UncachedWrite(
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2014-03-29 18:53:49 +01:00
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xact.addr,
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UInt(trackerId),
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2014-09-24 20:14:36 +02:00
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xact.data),
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{ case TLId => outerId })
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2014-04-30 01:49:18 +02:00
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io.inner.acquire.ready := Bool(false)
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io.inner.probe.valid := Bool(false)
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io.inner.release.ready := Bool(false)
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io.inner.grant.valid := Bool(false)
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io.inner.grant.bits.header.src := UInt(bankId)
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io.inner.grant.bits.header.dst := init_client_id
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2014-11-12 02:36:55 +01:00
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io.inner.grant.bits.payload := Grant(Bool(false),
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co.getGrantTypeOnVoluntaryWriteback(co.masterMetadataOnFlush),
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2014-03-29 18:53:49 +01:00
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xact.client_xact_id,
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UInt(trackerId))
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2013-01-29 01:39:45 +01:00
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switch (state) {
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is(s_idle) {
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2014-04-30 01:49:18 +02:00
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when( io.inner.release.valid ) {
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2014-11-12 21:55:07 +01:00
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io.inner.release.ready := Bool(true)
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xact := c_rel.payload
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init_client_id := c_rel.header.src
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state := Mux(co.messageHasData(c_rel.payload), s_mem, s_ack)
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2013-01-29 01:39:45 +01:00
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}
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}
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is(s_mem) {
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2014-04-30 01:49:18 +02:00
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io.outer.acquire.valid := Bool(true)
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when(io.outer.acquire.ready) { state := s_ack }
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2013-01-29 01:39:45 +01:00
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}
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is(s_ack) {
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2014-04-30 01:49:18 +02:00
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io.inner.grant.valid := Bool(true)
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when(io.inner.grant.ready) { state := s_idle }
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2013-01-29 01:39:45 +01:00
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}
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2013-01-17 08:57:35 +01:00
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}
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2013-01-29 01:39:45 +01:00
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}
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2013-01-17 08:57:35 +01:00
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2014-09-24 20:14:36 +02:00
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class AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends XactTracker(innerId, outerId) {
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2014-03-29 18:53:49 +01:00
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val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_busy :: Nil = Enum(UInt(), 6)
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2013-08-16 00:27:38 +02:00
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val state = Reg(init=s_idle)
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2013-01-22 02:17:26 +01:00
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val xact = Reg{ new Acquire }
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2014-08-08 21:21:57 +02:00
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val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
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2013-01-17 08:57:35 +01:00
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//TODO: Will need id reg for merged release xacts
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2014-03-29 18:53:49 +01:00
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2014-08-08 21:21:57 +02:00
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val release_count = if (nClients == 1) UInt(0) else Reg(init=UInt(0, width = log2Up(nClients)))
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val probe_flags = Reg(init=Bits(0, width = nClients))
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2013-03-26 00:20:12 +01:00
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val curr_p_id = PriorityEncoder(probe_flags)
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2014-03-29 18:53:49 +01:00
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val pending_outer_write = co.messageHasData(xact)
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2014-11-12 02:36:55 +01:00
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val pending_outer_read = co.requiresOuterRead(xact, co.masterMetadataOnFlush)
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val outer_write_acq = Bundle(UncachedWrite(xact.addr, UInt(trackerId), xact.data),
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{ case TLId => outerId })
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2014-11-12 21:55:07 +01:00
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val outer_write_rel = Bundle(UncachedWrite(xact.addr, UInt(trackerId), UInt(0)), // Special SQDId
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2014-11-12 02:36:55 +01:00
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{ case TLId => outerId })
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val outer_read = Bundle(UncachedRead(xact.addr, UInt(trackerId)),
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{ case TLId => outerId })
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2014-03-29 18:53:49 +01:00
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2014-08-08 21:21:57 +02:00
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val probe_initial_flags = Bits(width = nClients)
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2013-01-23 05:09:21 +01:00
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probe_initial_flags := Bits(0)
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2014-08-08 21:21:57 +02:00
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if (nClients > 1) {
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2013-01-17 08:57:35 +01:00
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// issue self-probes for uncached read xacts to facilitate I$ coherence
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2014-04-30 01:49:18 +02:00
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val probe_self = Bool(true) //co.needsSelfProbe(io.inner.acquire.bits.payload)
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2014-08-08 21:21:57 +02:00
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val myflag = Mux(probe_self, Bits(0), UIntToOH(c_acq.header.src(log2Up(nClients)-1,0)))
|
2013-01-23 05:09:21 +01:00
|
|
|
probe_initial_flags := ~(io.tile_incoherent | myflag)
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
|
2014-03-29 18:53:49 +01:00
|
|
|
io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) && (state != s_idle)
|
|
|
|
io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) && (state != s_idle)
|
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(false)
|
|
|
|
io.outer.acquire.bits.header.src := UInt(bankId)
|
|
|
|
//io.outer.acquire.bits.header.dst TODO
|
|
|
|
io.outer.acquire.bits.payload := outer_read
|
|
|
|
io.outer.grant.ready := io.inner.grant.ready
|
2014-03-29 18:53:49 +01:00
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.probe.valid := Bool(false)
|
|
|
|
io.inner.probe.bits.header.src := UInt(bankId)
|
|
|
|
io.inner.probe.bits.header.dst := curr_p_id
|
2014-11-05 23:21:38 +01:00
|
|
|
io.inner.probe.bits.payload := Probe(co.getProbeType(xact, co.masterMetadataOnFlush), xact.addr)
|
2014-03-29 18:53:49 +01:00
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.grant.valid := Bool(false)
|
|
|
|
io.inner.grant.bits.header.src := UInt(bankId)
|
|
|
|
io.inner.grant.bits.header.dst := init_client_id
|
2014-11-12 02:36:55 +01:00
|
|
|
io.inner.grant.bits.payload := Grant(xact.uncached,
|
|
|
|
co.getGrantType(xact, co.masterMetadataOnFlush),
|
2014-03-29 18:53:49 +01:00
|
|
|
xact.client_xact_id,
|
|
|
|
UInt(trackerId),
|
2014-11-12 21:55:07 +01:00
|
|
|
UInt(0)) // Data bypassed in parent
|
2014-03-29 18:53:49 +01:00
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.acquire.ready := Bool(false)
|
|
|
|
io.inner.release.ready := Bool(false)
|
2013-01-17 08:57:35 +01:00
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
is(s_idle) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.acquire.ready := Bool(true)
|
2014-03-29 18:53:49 +01:00
|
|
|
val needs_outer_write = co.messageHasData(c_acq.payload)
|
2014-11-12 02:36:55 +01:00
|
|
|
val needs_outer_read = co.requiresOuterRead(c_acq.payload, co.masterMetadataOnFlush)
|
2014-04-30 01:49:18 +02:00
|
|
|
when( io.inner.acquire.valid ) {
|
2014-03-29 18:53:49 +01:00
|
|
|
xact := c_acq.payload
|
|
|
|
init_client_id := c_acq.header.src
|
2013-01-23 05:09:21 +01:00
|
|
|
probe_flags := probe_initial_flags
|
2014-08-08 21:21:57 +02:00
|
|
|
if(nClients > 1) {
|
2013-01-23 05:09:21 +01:00
|
|
|
release_count := PopCount(probe_initial_flags)
|
2014-03-29 18:53:49 +01:00
|
|
|
state := Mux(probe_initial_flags.orR, s_probe,
|
|
|
|
Mux(needs_outer_write, s_mem_write,
|
|
|
|
Mux(needs_outer_read, s_mem_read, s_make_grant)))
|
|
|
|
} else state := Mux(needs_outer_write, s_mem_write,
|
|
|
|
Mux(needs_outer_read, s_mem_read, s_make_grant))
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_probe) {
|
2014-03-29 18:53:49 +01:00
|
|
|
// Generate probes
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.probe.valid := probe_flags.orR
|
|
|
|
when(io.inner.probe.ready) {
|
2013-08-12 19:36:44 +02:00
|
|
|
probe_flags := probe_flags & ~(UIntToOH(curr_p_id))
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2014-03-29 18:53:49 +01:00
|
|
|
|
|
|
|
// Handle releases, which may have data to be written back
|
2014-04-30 01:49:18 +02:00
|
|
|
when(io.inner.release.valid) {
|
2014-03-29 18:53:49 +01:00
|
|
|
when(co.messageHasData(c_rel.payload)) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
io.outer.acquire.bits.payload := outer_write_rel
|
|
|
|
when(io.outer.acquire.ready) {
|
|
|
|
io.inner.release.ready := Bool(true)
|
2014-08-08 21:21:57 +02:00
|
|
|
if(nClients > 1) release_count := release_count - UInt(1)
|
2014-03-29 18:53:49 +01:00
|
|
|
when(release_count === UInt(1)) {
|
|
|
|
state := Mux(pending_outer_write, s_mem_write,
|
|
|
|
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} .otherwise {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.release.ready := Bool(true)
|
2014-08-08 21:21:57 +02:00
|
|
|
if(nClients > 1) release_count := release_count - UInt(1)
|
2014-03-29 18:53:49 +01:00
|
|
|
when(release_count === UInt(1)) {
|
|
|
|
state := Mux(pending_outer_write, s_mem_write,
|
|
|
|
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
|
|
|
}
|
2013-04-10 22:46:31 +02:00
|
|
|
}
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2014-03-29 18:53:49 +01:00
|
|
|
}
|
|
|
|
is(s_mem_read) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
io.outer.acquire.bits.payload := outer_read
|
|
|
|
when(io.outer.acquire.ready) {
|
2014-11-12 02:36:55 +01:00
|
|
|
state := Mux(co.requiresAckForGrant(io.inner.grant.bits.payload), s_busy, s_idle)
|
2013-04-30 03:47:37 +02:00
|
|
|
}
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2014-03-29 18:53:49 +01:00
|
|
|
is(s_mem_write) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
io.outer.acquire.bits.payload := outer_write_acq
|
|
|
|
when(io.outer.acquire.ready) {
|
2014-03-29 18:53:49 +01:00
|
|
|
state := Mux(pending_outer_read, s_mem_read, s_make_grant)
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
2014-03-29 18:53:49 +01:00
|
|
|
is(s_make_grant) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.grant.valid := Bool(true)
|
|
|
|
when(io.inner.grant.ready) {
|
2014-11-12 02:36:55 +01:00
|
|
|
state := Mux(co.requiresAckForGrant(io.inner.grant.bits.payload), s_busy, s_idle)
|
2014-03-29 18:53:49 +01:00
|
|
|
}
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
is(s_busy) { // Nothing left to do but wait for transaction to complete
|
2014-04-30 01:49:18 +02:00
|
|
|
when(io.outer.grant.valid && m_gnt.payload.client_xact_id === UInt(trackerId)) {
|
|
|
|
io.inner.grant.valid := Bool(true)
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2014-04-30 01:49:18 +02:00
|
|
|
when(io.inner.finish.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
|
2014-03-29 18:53:49 +01:00
|
|
|
state := s_idle
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|