riscv/sifive-blocks
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  • 9ba47b76c6 MockAON: Accept the non-debug interrupt as an input to overall reset. Megan Wachs 2017-04-07 16:42:32 -0700
  • dbd16e305d Merge pull request #6 from sifive/debug_v013 Megan Wachs 2017-03-31 15:14:35 -0700
  • 70ac4044d1 spi: correct polarity of FIRRTL combo loop detection workaround. Megan Wachs 2017-03-31 13:49:34 -0700
  • 1af6ce1c85 Merge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD Megan Wachs 2017-03-30 20:01:30 -0700
  • 6a3b5e1a31 "Fix" false combinational loop through SPIArbiter Jack Koenig 2017-03-30 19:12:15 -0700
  • 3f6f10f4ed Merge remote-tracking branch 'origin/master' into debug-0.13 Megan Wachs 2017-03-27 18:48:24 -0700
  • 3c2277447d rename l2FrontendBus as fsb Yunsup Lee 2017-03-24 21:38:31 -0700
  • e2073feef8 rename l2FrontendBus as fsb Yunsup Lee 2017-03-24 21:38:31 -0700
  • faeb14dc5a JTAG: make TRSTn optional for all helpers as well to match the IO. Megan Wachs 2017-03-24 17:27:55 -0700
  • 2c47cc4abd Merge remote-tracking branch 'origin/master' into debug-0.13 Megan Wachs 2017-03-22 19:16:20 -0700
  • c1872c574b update TLRegisterNode to take Seq of AddressSet Yunsup Lee 2017-03-21 22:12:37 -0700
  • c6d7326669 TLSPI: address parameter must now be a sequence. Megan Wachs 2017-03-21 17:51:28 -0700
  • 77246eaada Adjust JTAG for rocket-chip changes Megan Wachs 2017-03-14 14:52:39 -0700
  • 25356957fe Merge remote-tracking branch 'origin/master' into debug-0.13 Megan Wachs 2017-03-10 14:09:24 -0800
  • 062203ae18 xilinx pcie: add the high PCIe address bits (physical path) Wesley W. Terpstra 2017-03-02 21:22:41 -0800
  • 64bff44462 Merge pull request #4 from sifive/periphery-keys Wesley W. Terpstra 2017-03-02 21:00:44 -0800
  • 46aa6b0ac4 devices: include DTS meta-data Wesley W. Terpstra 2017-03-02 20:28:38 -0800
  • baccd5ada2 devices: create periphery keys for all devices Wesley W. Terpstra 2017-02-22 18:42:47 -0800
  • bf9b81f2bc jtag: The jtag interfaces have moved to a different package. Megan Wachs 2017-03-02 14:46:34 -0800
  • 072d0c1b58 Merge pull request #2 from sifive/homogenous_bag_peripherals Megan Wachs 2017-02-16 18:45:48 -0800
  • 03be9aba67 Use HomogenousBag to handle lists of peripherals Megan Wachs 2017-02-16 17:52:24 -0800
  • 348bbb97f4 Merge pull request #1 from sifive/i2c solomatnikov 2017-02-10 14:30:01 -0800
  • a915e84a9e Merge remote-tracking branch 'origin/master' into i2c Alex Solomatnikov 2017-02-09 18:45:35 -0800
  • 095cb158dd Flipped polarity of output enables to match Guava pins logic Alex Solomatnikov 2017-02-09 11:37:40 -0800
  • 72e4b60d81 Made regs 32-bit word aligned to match the rest of the system Alex Solomatnikov 2017-02-09 11:36:19 -0800
  • 9ca71c0cf2 Added note: WISHBONE interface replaced by Tilelink2 Alex Solomatnikov 2017-02-07 16:14:28 -0800
  • c311b6ec63 Added license Alex Solomatnikov 2017-02-07 15:58:04 -0800
  • 5a0d084b38 Renamed i2cDevices to i2c Alex Solomatnikov 2017-02-06 10:39:47 -0800
  • 88e4c8ee20 xilinx mig: track changes in rocket-chip Wesley W. Terpstra 2017-02-03 18:17:58 -0800
  • d474b5ceb2 Addressing comments: bool style, comments, removed suggestName Alex Solomatnikov 2017-02-03 18:10:03 -0800
  • 3781d1fb1a Bug fixes: passing OC WB test Alex Solomatnikov 2017-02-03 16:41:59 -0800
  • c010a1557a sifive-blocks: trust diplomacy to get names right Wesley W. Terpstra 2017-02-01 13:53:54 -0800
  • 2cc1012fa2 Completed Chisel RTL (not tested yet) Alex Solomatnikov 2017-01-31 17:20:53 -0800
  • 535be3e976 spi: work around ucb-bar/chisel3#472 Wesley W. Terpstra 2017-01-31 14:03:14 -0800
  • 5b6760394d xilinx ip: adjust to new diplomacy API Wesley W. Terpstra 2017-01-30 11:33:30 -0800
  • 9d2a173b15 Initial (compilable) version of I2C (no actual logic yet) Alex Solomatnikov 2017-01-24 14:58:01 -0800
  • d61d86e084 xilinx pcie: put buffers before the outputs to the controller Wesley W. Terpstra 2017-01-20 22:38:27 -0800
  • c68e44ec55 mig: track change to Blind port API in rocket Wesley W. Terpstra 2017-01-19 19:53:03 -0800
  • 45c491cd69 LazyModule: provide Parameters Wesley W. Terpstra 2016-12-07 13:21:20 -0800
  • 1443834186 xilinx pcie: bytes, not bits Wesley W. Terpstra 2016-12-06 16:13:12 -0800
  • ca7555bd4d RegMapFIFO: amoor.w can do thread-safe TX Wesley W. Terpstra 2016-12-02 17:48:17 -0800
  • b8ecb7853b Add /target to .gitignore. Richard Xia 2016-11-30 13:29:54 -0800
  • 7916ef5249 Initial commit. SiFive 2016-11-29 04:08:44 -0800