Andrew Waterman 2e88ffc364 Cope with changes to AddrMap

2016-06-03 13:48:09 -07:00

..

ahb.scala

Ahb tweaks (#50)

2016-06-01 16:42:39 -07:00

amoalu.scala

ahb: amoalu does not need so many parameters! (i want to reuse it)

2016-05-24 14:58:27 -07:00

bram.scala

fix HastiRAM

2016-06-01 10:33:59 -07:00

broadcast.scala

fix BroadcastHub allocation and routing

2016-04-05 16:21:18 -07:00

builder.scala

Add config classes to drive unit testing of L2 TileLink agents.

2016-05-20 16:15:43 -07:00

cache.scala

Work around PutBlocks draining into data array prematurely

2016-05-26 23:08:05 -07:00

coherence.scala

fix more Chisel3 deprecations

2016-01-14 14:55:45 -08:00

consts.scala

Add M_FLUSH_ALL command

2016-05-31 19:25:31 -07:00

converters.scala

Add generic TileLink width adapter

2016-05-26 15:59:42 -07:00

debug.scala

Can't assign to Vec literals

2016-06-01 23:36:34 -07:00

directory.scala

First pages commit

2015-04-29 13:18:26 -07:00

dma.scala

make sure CSR width is parameterizable

2016-02-02 12:49:58 -08:00

ecc.scala

Avoid floating-point arithmetic where integers suffice

2016-06-01 21:59:02 -07:00

htif.scala

Work around zero-width wire limitation in HTIF

2016-05-25 20:39:53 -07:00

interconnect.scala

Cope with changes to AddrMap

2016-06-03 13:48:09 -07:00

metadata.scala

Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.

2016-03-10 17:14:34 -08:00

network.scala

Use buses, rather than crossbars, by default in TLInterconnect

2016-05-26 16:10:42 -07:00

package.scala

First pages commit

2015-04-29 13:18:26 -07:00

plic.scala

Allow PLIC nPriorities=0 (priority fixed at 1)

2016-06-02 13:48:29 -07:00

prci.scala

Add trivial version of PRCI block

2016-05-02 17:49:10 -07:00

rom.scala

Fix arithmetic in ROM row count

2016-06-01 21:59:02 -07:00

rtc.scala

rtc: fix acquire message type check

2016-05-25 20:37:48 -07:00

scr.scala

print the base address of each SCR as indicated

2016-04-28 16:31:56 +01:00

tilelink.scala

Work around another zero-width wire limitation

2016-05-25 21:42:02 -07:00

uncore.scala

Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release,

2016-05-20 16:35:30 -07:00

util.scala

Avoid floating-point arithmetic where integers suffice

2016-06-01 21:59:02 -07:00