| .. |
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arbiter.scala
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Don't rely on tag value for nacks
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2016-05-24 15:05:41 -07:00 |
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breakpoint.scala
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Refactor breakpoints and support range comparison (currently disabled)
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2016-06-10 19:55:58 -07:00 |
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btb.scala
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Remove dead code from BTB
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2016-04-27 00:28:12 -07:00 |
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consts.scala
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WIP on priv spec v1.9
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2016-03-02 23:29:58 -08:00 |
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csr.scala
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Add D-mode single-step support
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2016-06-15 16:21:24 -07:00 |
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dcache.scala
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Fix D$ for set size > page size
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2016-06-09 13:02:28 -07:00 |
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decode.scala
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Use Seq, not Iterable, when traversal order matters
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2015-07-29 00:24:58 -07:00 |
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dma.scala
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Cope with changes to AddrMap
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2016-06-03 13:50:29 -07:00 |
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dpath_alu.scala
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Improve ALU QoR
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2016-01-20 17:42:31 -08:00 |
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fpu.scala
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remove implicit modulo addressing in FPU (#44)
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2016-06-09 11:33:33 -07:00 |
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frontend.scala
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Support larger I$ sets when VM is disabled
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2016-05-24 15:44:59 -07:00 |
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icache.scala
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Support larger I$ sets when VM is disabled
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2016-05-24 15:44:59 -07:00 |
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idecode.scala
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First stab at debug interrupts
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2016-06-01 16:57:10 -07:00 |
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instructions.scala
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Add provisional breakpoint support
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2016-06-08 20:19:52 -07:00 |
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multiplier.scala
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Remove unnecessary muxes in RV32 MulDiv
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2016-05-25 14:27:02 -07:00 |
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nbdcache.scala
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pass invalidate_lr through simple cache interface (#45)
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2016-06-09 17:22:36 -07:00 |
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package.scala
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make mtvec configurable and writeable
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2016-01-29 14:51:56 -08:00 |
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ptw.scala
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Handle invalidate_lr in cache arbiter, not tile
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2016-04-27 11:22:04 -07:00 |
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rocc.scala
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set invalidate_lr in other rocc examples (#47)
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2016-06-14 16:59:37 -07:00 |
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rocket.scala
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Add D-mode single-step support
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2016-06-15 16:21:24 -07:00 |
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tile.scala
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Instantiate blocking D$ when NMSHRS=0
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2016-05-24 15:05:41 -07:00 |
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tlb.scala
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First stab at debug interrupts
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2016-06-01 16:57:10 -07:00 |
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util.scala
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Get rid of unused implicit conversion
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2016-06-01 19:30:41 -07:00 |
