Andrew Waterman 0b4c8e9af7 Add D-mode single-step support

2016-06-15 16:21:24 -07:00

..

arbiter.scala

Don't rely on tag value for nacks

2016-05-24 15:05:41 -07:00

breakpoint.scala

Refactor breakpoints and support range comparison (currently disabled)

2016-06-10 19:55:58 -07:00

btb.scala

Remove dead code from BTB

2016-04-27 00:28:12 -07:00

consts.scala

WIP on priv spec v1.9

2016-03-02 23:29:58 -08:00

csr.scala

Add D-mode single-step support

2016-06-15 16:21:24 -07:00

dcache.scala

Fix D$ for set size > page size

2016-06-09 13:02:28 -07:00

decode.scala

Use Seq, not Iterable, when traversal order matters

2015-07-29 00:24:58 -07:00

dma.scala

Cope with changes to AddrMap

2016-06-03 13:50:29 -07:00

dpath_alu.scala

Improve ALU QoR

2016-01-20 17:42:31 -08:00

fpu.scala

remove implicit modulo addressing in FPU (#44)

2016-06-09 11:33:33 -07:00

frontend.scala

Support larger I$ sets when VM is disabled

2016-05-24 15:44:59 -07:00

icache.scala

Support larger I$ sets when VM is disabled

2016-05-24 15:44:59 -07:00

idecode.scala

First stab at debug interrupts

2016-06-01 16:57:10 -07:00

instructions.scala

Add provisional breakpoint support

2016-06-08 20:19:52 -07:00

multiplier.scala

Remove unnecessary muxes in RV32 MulDiv

2016-05-25 14:27:02 -07:00

nbdcache.scala

pass invalidate_lr through simple cache interface (#45)

2016-06-09 17:22:36 -07:00

package.scala

make mtvec configurable and writeable

2016-01-29 14:51:56 -08:00

ptw.scala

Handle invalidate_lr in cache arbiter, not tile

2016-04-27 11:22:04 -07:00

rocc.scala

set invalidate_lr in other rocc examples (#47)

2016-06-14 16:59:37 -07:00

rocket.scala

Add D-mode single-step support

2016-06-15 16:21:24 -07:00

tile.scala

Instantiate blocking D$ when NMSHRS=0

2016-05-24 15:05:41 -07:00

tlb.scala

First stab at debug interrupts

2016-06-01 16:57:10 -07:00

util.scala

Get rid of unused implicit conversion

2016-06-01 19:30:41 -07:00