riscv/rocket-chip
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  • d811692c3b Mitigate I$->D$->I$ critical path Andrew Waterman 2017-07-31 01:43:04 -0700
  • ea1840c4b1 Merge pull request #904 from freechipsproject/fix-dcache-bug Yunsup Lee 2017-07-29 20:30:47 -0700
  • ac4339a8e7 Pass D$ backpressure to D-channel, rather than asserting Andrew Waterman 2017-07-29 11:48:36 -0700
  • edcd2c696c Avoid needless stall on E-channel back pressure Andrew Waterman 2017-07-29 11:47:58 -0700
  • 8e2e931770 Merge pull request #903 from freechipsproject/monitor-probes Wesley W. Terpstra 2017-07-29 01:12:08 -0700
  • 56e28026a6 TLError: does not need to be fast; cut the loop Wesley W. Terpstra 2017-07-29 00:22:21 -0700
  • 540256e24a systembus: all slaves should have an output buffer Wesley W. Terpstra 2017-07-29 00:13:33 -0700
  • eadf4e9fcc Revert "tile: add option for tile boundary buffers" Wesley W. Terpstra 2017-07-29 00:03:24 -0700
  • 68064ba260 systembus: don't double down on buffers Wesley W. Terpstra 2017-07-29 00:01:26 -0700
  • 140086e2c5 Merge pull request #902 from freechipsproject/perf-improvements Yunsup Lee 2017-07-28 20:12:10 -0700
  • a0db929003 tilelink: use the Monitor to enforce Probe sourcing Wesley W. Terpstra 2017-07-28 18:08:00 -0700
  • 573890e102 Merge pull request #900 from freechipsproject/more_verbose_requires Megan Wachs 2017-07-28 13:23:33 -0700
  • fdb8935712 Improve fidelity of two perf counters Andrew Waterman 2017-07-28 13:14:04 -0700
  • 4c82f6b77e Don't refill BTB on not-taken branches Andrew Waterman 2017-07-28 13:13:52 -0700
  • 2e8b02e780 Merge D$ store hits when ECC is enabled Andrew Waterman 2017-07-27 23:33:39 -0700
  • 838864870e Bypass TLB refill signal to halve L2 TLB hit time Andrew Waterman 2017-07-26 16:55:45 -0700
  • ae1f7a95f6 Don't nack misses when there's a pending store Andrew Waterman 2017-07-26 15:09:17 -0700
  • 7eeb9dfd88 Merge pull request #899 from freechipsproject/wrapper-dedup Henry Cook 2017-07-28 10:52:59 -0700
  • f61fe2be1e diplomacy: More verbose require Megan Wachs 2017-07-28 10:05:45 -0700
  • 370cc392e0 Merge pull request #898 from freechipsproject/uncached-acquire Wesley W. Terpstra 2017-07-27 22:14:53 -0700
  • 5f81c2243f tilelink: add BusBypass, useful to turn devices off Wesley W. Terpstra 2017-07-27 14:56:15 -0700
  • 9a36755b6a tilelink: CacheCork uses constructor helpers Wesley W. Terpstra 2017-07-27 18:22:06 -0700
  • 45189c3e30 tilelink: CacheCork now supports errors and BtoT upgrade Wesley W. Terpstra 2017-07-27 14:07:24 -0700
  • 2e4f1611ed tilelink: Error device supports Acquire Wesley W. Terpstra 2017-07-27 11:10:34 -0700
  • b64b87ad07 tile: add option for tile boundary buffers Henry Cook 2017-07-27 17:30:51 -0700
  • 289ef30dbc coreplex: change AsynchronousCrossing.sync default to 3 Henry Cook 2017-07-27 15:44:51 -0700
  • 266ed56e8d tile: turn off more slave port monitors Henry Cook 2017-07-27 15:28:53 -0700
  • 9a483af6e8 coreplex: naming of tile wrappers Henry Cook 2017-07-27 15:16:48 -0700
  • 33852ef965 coreplex: remove superfluous sink and source from wrapper Henry Cook 2017-07-27 14:23:03 -0700
  • 651da73d89 tilelink: it is now legal to support Acquire for UNCACHED regions Wesley W. Terpstra 2017-07-27 00:25:07 -0700
  • 0ab5cb67b3 tilelink: fix RAMModel handling of AMOs on early source reuse (#897) Wesley W. Terpstra 2017-07-27 11:07:13 -0700
  • 9804bdc34e tilelink: remove obsolete addr_lo signal (#895) Wesley W. Terpstra 2017-07-26 16:01:21 -0700
  • 3cceb866cf Merge pull request #896 from freechipsproject/fuzzer-rage Wesley W. Terpstra 2017-07-26 16:01:07 -0700
  • d096d5d1c4 tilelink: fix AtomicAutomata bug wrt early source reuse Wesley W. Terpstra 2017-07-26 12:52:29 -0700
  • 6550ae2e31 tilelink: increase Fuzzer source reuse aggression Wesley W. Terpstra 2017-07-26 11:57:24 -0700
  • 1efdca106c tilelink: RAMModel support early reuse of source Wesley W. Terpstra 2017-07-26 10:50:47 -0700
  • 138276fd87 tilelink: SourceShrinker should work also for 0 latency Wesley W. Terpstra 2017-07-26 10:40:40 -0700
  • f02c921d0f Merge pull request #893 from freechipsproject/width-update Wesley W. Terpstra 2017-07-26 12:35:51 -0700
  • b2edca2a6b tilelink: cut WidthWidget from dependency on addr_lo Wesley W. Terpstra 2017-07-25 19:09:54 -0700
  • ede87c1f73 tilelink: rewrite WidthWidget beat splitter Wesley W. Terpstra 2017-07-25 18:35:06 -0700
  • 0f5065fbf3 tilelink: WidthWidget rewrite beat merging Wesley W. Terpstra 2017-07-25 16:54:30 -0700
  • f0ffb7e31e tilelink: initialize toggle in Fragmenter (#894) Wesley W. Terpstra 2017-07-26 10:21:31 -0700
  • 27d5557177 Merge pull request #891 from freechipsproject/fix-l2-tlb Andrew Waterman 2017-07-26 09:43:16 -0700
  • 5a5b78b15e Improve L2 TLB coding style Andrew Waterman 2017-07-26 02:22:43 -0700
  • 5a9c673f41 Fix L2 TLB response bug Andrew Waterman 2017-07-26 02:20:41 -0700
  • acca0fccf5 Fix BTB not being refilled on some indirect jumps Andrew Waterman 2017-07-26 02:13:43 -0700
  • 6916e5cbfb coreplex: better names for RocketTiles in Verilog (#890) Yunsup Lee 2017-07-25 16:35:31 -0700
  • d43f02268b Merge pull request #889 from freechipsproject/acq-before-rel-and-jump-in-frontend Andrew Waterman 2017-07-25 16:26:47 -0700
  • c2b8b08461 tilelink: fix Fragmenter source re-use bug (#888) Wesley W. Terpstra 2017-07-25 16:23:55 -0700
  • 15878d4691 Perform some control-flow transfers within the Frontend Andrew Waterman 2017-07-25 15:18:32 -0700
  • 62c4080585 Add RVC instruction patterns Andrew Waterman 2017-07-25 15:17:26 -0700
  • 66d06460fa Add option for acquire-before-release Andrew Waterman 2017-07-25 15:16:09 -0700
  • 86ccd935fc Add method to print perf events Andrew Waterman 2017-07-25 15:14:15 -0700
  • 5df8f0d1ea Add L2 TLB miss counter Andrew Waterman 2017-07-25 11:59:53 -0700
  • 3ced04b70a Mix in trait to connect global_reset_vector Andrew Waterman 2017-07-25 11:57:58 -0700
  • c9e467a668 coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency (#887) Yunsup Lee 2017-07-25 00:55:55 -0700
  • 68ed055f6d chiplink: adjust bus view to include the splitter (#886) Wesley W. Terpstra 2017-07-24 21:41:17 -0700
  • dc435af30a fix HasRTCModuleImp (#885) Yunsup Lee 2017-07-24 20:24:59 -0700
  • 01ca3efc2b Combine Coreplex and System Module Hierarchies (#875) Henry Cook 2017-07-23 08:31:04 -0700
  • f2002839eb TLFragmenter: Continuing my spot battles on requires without explanatory strings (#882) Megan Wachs 2017-07-21 21:55:32 -0700
  • cf75c2049d Merge pull request #878 from freechipsproject/fix-fifofixer Yunsup Lee 2017-07-19 20:22:16 -0700
  • 21954c1c73 tileink: FIFOFixer should cope with zero-latency devices Yunsup Lee 2017-07-19 19:38:27 -0700
  • 4d784ad693 add cloneType to RegisterWriteIO and RegisterReadIO (#874) Howard Mao 2017-07-18 18:52:31 -0700
  • 8d793daf9c Merge pull request #876 from freechipsproject/sq-helper Wesley W. Terpstra 2017-07-18 16:30:23 -0700
  • a9c58e9d9f diplomacy: support creating ShiftQueues as well Wesley W. Terpstra 2017-07-18 14:20:26 -0700
  • c0a3bb58e9 ShiftQueue: use Vec of Bool to support constant prop of enq.valid Wesley W. Terpstra 2017-07-18 14:20:04 -0700
  • 6d0821f19a Update readme to reflect config name changes (#871) Colin Schmidt 2017-07-18 07:27:03 -0700
  • 416629b3bf tilelink: FIFOFixer should fix no domain => domain cases (#873) Wesley W. Terpstra 2017-07-17 22:32:17 -0700
  • d09a985729 zero: fix attachment in multichannel case (#870) Wesley W. Terpstra 2017-07-17 21:48:31 -0700
  • fc75ada577 tilelink: Monitor should report line numbers of connection that failed (#872) Wesley W. Terpstra 2017-07-17 21:29:14 -0700
  • ec57994784 fix the TLFuzzer IO (#869) Howard Mao 2017-07-17 14:59:35 -0700
  • 16e8709144 tilelink: it is now legal to have errors on {Release,Hint}Ack (#864) Wesley W. Terpstra 2017-07-14 16:13:30 -0700
  • 9ade7af013 Merge pull request #862 from freechipsproject/plic-max-pri-dts Richard Xia 2017-07-13 17:08:21 -0700
  • f0481801df Merge pull request #863 from freechipsproject/rename-offchip-interrupts-to-external-interrupts Richard Xia 2017-07-13 16:52:57 -0700
  • 35464782b5 PLIC: maxPriorities comes from params Megan Wachs 2017-07-13 15:57:10 -0700
  • d62787357b Rename offchip-interrupts to external-interrupts. Richard Xia 2017-07-13 15:56:22 -0700
  • f2533ce825 bootrom: Adding bootrom parameters (#857) Shreesha Srinath 2017-07-13 13:40:02 -0700
  • f646bed3ea PLIC: Use longer DTS name for Max Priorities. Megan Wachs 2017-07-13 13:37:22 -0700
  • 0800fd3ed9 PLIC: Add maxPri as well as ndev in DTS Megan Wachs 2017-07-13 13:18:50 -0700
  • b7f1ba3428 tilelink: FIFOFixer must support null cases (#860) Wesley W. Terpstra 2017-07-12 22:20:31 -0700
  • 0053a060ae Merge pull request #859 from freechipsproject/fifo-fixer-configable Wesley W. Terpstra 2017-07-12 19:44:23 -0700
  • 4eface8a9e rocket: do not require FIFO order for memory-like regions Wesley W. Terpstra 2017-07-12 16:20:22 -0700
  • 09b9d33a9a tilelink: FIFOFixer now has a policy parameter Wesley W. Terpstra 2017-07-12 13:55:31 -0700
  • b363a94480 diplomacy: add a new UNCACHEABLE RegionType Wesley W. Terpstra 2017-07-12 16:19:19 -0700
  • c8a7648169 diplomacy: only evaluate a Nexus node's map function once Wesley W. Terpstra 2017-07-12 15:03:17 -0700
  • af3976aa67 regmapper: add byte-sized RegField helper function (#854) Wesley W. Terpstra 2017-07-10 21:08:02 -0700
  • 177ccbb663 regfield: More explanatory requires so I don't have to RTFC and figure out what width actually was (#855) Megan Wachs 2017-07-10 21:07:50 -0700
  • 287219da06 Merge pull request #851 from freechipsproject/chisel3clock Jim Lawson 2017-07-10 08:33:46 -0700
  • 29f5f77817 Merge pull request #853 from freechipsproject/sram-errors Wesley W. Terpstra 2017-07-07 22:44:28 -0700
  • 5db0e770d5 tilelink: TestSRAM can emulate incompletely populated memory Wesley W. Terpstra 2017-07-07 21:13:48 -0700
  • 702143eb33 tilelink: SRAM can emulate incompletely populated memory Wesley W. Terpstra 2017-07-07 21:08:14 -0700
  • 9310a33e77 apb: SRAM can emulate incompletely populated memory Wesley W. Terpstra 2017-07-07 21:08:07 -0700
  • 28fbf1af8e ahb: SRAM can emulate incompletely populated memory Wesley W. Terpstra 2017-07-07 21:07:58 -0700
  • df44b23956 axi4: SRAM can emulate incompletely populated memory Wesley W. Terpstra 2017-07-07 21:07:08 -0700
  • b2cc4b99ed tilelink: TestSRAM reports errors on illegal access Wesley W. Terpstra 2017-07-07 21:13:07 -0700
  • e8cb6dafd3 tilelink: SRAM reports errors on illegal access Wesley W. Terpstra 2017-07-07 21:04:05 -0700
  • f1fb3be603 ahb: SRAM reports errors on illegal access Wesley W. Terpstra 2017-07-07 19:39:03 -0700
  • 19851a7c9e apb: SRAM reports errors on illegal access Wesley W. Terpstra 2017-07-07 19:38:45 -0700
  • 025f7d890b axi4: SRAM now reports errors on illegal address (#852) Wesley W. Terpstra 2017-07-07 19:27:32 -0700
  • 2bf91a0558 Use chisel3 Clock() method. Jim Lawson 2017-07-07 14:16:39 -0700