riscv/rocket-chip
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  • ab3219cf6e don't use Scala to Chisel implicit conversions outside of rocket Howard Mao 2016-09-28 16:10:32 -0700
  • 9910c69c67 Move a bunch more things into util package Howard Mao 2016-09-27 21:27:07 -0700
  • e928b741ce Default mtvec=0, not None Andrew Waterman 2016-09-29 13:52:41 -0700
  • 1e43512142 jtag: Actually apply the sticky bits Megan Wachs 2016-09-27 16:22:55 -0700
  • a4b81aebe0 jtag: Apply sticky bits for error and busy according to the current Debug Spec Megan Wachs 2016-09-27 13:26:10 -0700
  • fc4d6ed0c6 jtag: clean up debug flags in regression/Makefile Megan Wachs 2016-09-27 11:27:22 -0700
  • 45bd63fcc6 jtag: Prevent Debug RAM accesses from wrapping around, and bring the DTM closer to the Debug Spec Megan Wachs 2016-09-27 10:48:04 -0700
  • 449d689a4e jtag: Connect the JTAG DTM side of the synchronizer! Megan Wachs 2016-09-26 20:28:26 -0700
  • 0924f8adb0 print out assigned inerrupt ranges Yunsup Lee 2016-09-28 20:33:24 -0700
  • 4c3e8ec1b4 assign interrupt ranges deterministically Yunsup Lee 2016-09-28 20:32:53 -0700
  • 4ac0ef2940 bump torture pointer after sim name change Colin Schmidt 2016-09-29 10:08:44 -0700
  • 7bca99a27a [tilelink2] Add unit test configs to regression Henry Cook 2016-09-28 17:15:12 -0700
  • 32f3f94882 [tilelink2] Fix zero-width wires in RAMModel. Henry Cook 2016-09-28 16:52:08 -0700
  • 69e121260e [tilelink2] Add unit tests for many TL2 components Henry Cook 2016-09-28 15:11:05 -0700
  • 81123f84c9 [tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. (#356) Henry Cook 2016-09-27 18:06:21 -0700
  • c45cc76cef Get rid of remaining MemIO code Howard Mao 2016-09-27 15:11:31 -0700
  • 18e7ea89f2 Get rid of broken groundtests Howard Mao 2016-09-27 13:20:08 -0700
  • c77c244016 Get rid of NASTI memory interconnects Howard Mao 2016-09-27 13:13:22 -0700
  • 7d93fd3bfc Merge pull request #354 from ucb-bar/async_register_crossing Howard Mao 2016-09-27 16:27:42 -0700
  • f9e0a7ac24 Merge branch 'master' into async_register_crossing mwachs5 2016-09-27 15:54:34 -0700
  • 3926cb936b rocketchip: add pbus width and AMO With classes (#357) Wesley W. Terpstra 2016-09-27 15:52:13 -0700
  • eaea138d0d tilelink2: don't use chisel3 namespace (#355) Wesley W. Terpstra 2016-09-27 14:44:26 -0700
  • f5502df6ab Merge branch 'master' into async_register_crossing Henry Cook 2016-09-27 14:08:27 -0700
  • 357d06ac9c tilelink2 WidthWidget: Gets must have their mask adjusted (#353) Wesley W. Terpstra 2016-09-27 14:06:02 -0700
  • 3ce08f40a5 crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations Megan Wachs 2016-09-27 13:36:28 -0700
  • 71a9c78e4b add WidthAdapter from AXI slave to Coreplex TL slave Howard Mao 2016-09-27 12:07:02 -0700
  • 7d6fb950b6 Give TileLink IDs more sensible names Howard Mao 2016-09-27 11:44:11 -0700
  • 8a55521b01 move memory width adapter from coreplex to periphery Howard Mao 2016-09-27 11:33:20 -0700
  • e36441a046 use correct parameters object for MMIO width adapter Howard Mao 2016-09-27 11:13:07 -0700
  • 201e247f73 Factor coreplex IO connection into separate trait (#350) Howard Mao 2016-09-27 11:55:32 -0700
  • 6316ebd58f make naming of L2toMC parameter object consistent between coreplex and periphery Howard Mao 2016-09-26 15:57:24 -0700
  • ea9f0a868f TileLink utility objects should not take implicit parameters Howard Mao 2016-09-23 10:06:09 -0700
  • 803739a95c Make sure coreplex mmio's TLId is correct (thanks to zizztux) Howard Mao 2016-09-23 00:19:08 -0700
  • c741ada619 get TraceGen working again Howard Mao 2016-09-22 23:53:07 -0700
  • 10df142ac7 fix emulator path to use PROJECT instead of MODEL Howard Mao 2016-09-22 21:17:00 -0700
  • d9e209365d Tl2 addr width0 (#346) Wesley W. Terpstra 2016-09-26 17:00:03 -0700
  • 72c205b54f tilelink2 AddressSet: add .misaligned(low, size) helper method (#345) Wesley W. Terpstra 2016-09-26 16:01:09 -0700
  • dd9558f45d rocketchip: generate GraphML output Wesley W. Terpstra 2016-09-26 01:42:46 -0700
  • 1773eb4405 tilelink2 LazyModule: output GraphML of the bus Wesley W. Terpstra 2016-09-26 01:19:28 -0700
  • 35da9320bc tilelink2 Nodes: expose connectivity in RootNode Wesley W. Terpstra 2016-09-26 01:18:53 -0700
  • 14cd39e045 rocketchip: rename identically names devices with _%d (#340) Wesley W. Terpstra 2016-09-26 13:05:49 -0700
  • 77a0f76289 Cleanup jtag dtm (#342) mwachs5 2016-09-26 11:10:27 -0700
  • 8641639873 Async rst async queue (#336) mwachs5 2016-09-26 11:08:38 -0700
  • d787bae0d0 tilelink2 Xbar: decouple ready from valid (#338) Wesley W. Terpstra 2016-09-23 16:24:29 -0700
  • d175bb314d Periphery: make bus width and arithmetic atomics configurable (#337) Wesley W. Terpstra 2016-09-23 15:25:58 -0700
  • 47843d8ec1 tilelink2: maxLgSize should be accurate (#332) Wesley W. Terpstra 2016-09-22 22:06:22 -0700
  • 7ee79efc15 Merge pull request #333 from ucb-bar/tl2-api-changes Wesley W. Terpstra 2016-09-22 21:20:27 -0700
  • c5706afc11 RegField: remove obsolete split method Wesley W. Terpstra 2016-09-22 20:00:49 -0700
  • fc44151f10 RegField: add name and description fields Wesley W. Terpstra 2016-09-22 19:59:35 -0700
  • 5e34b313ee RegMapper: regmap(...) now takes BYTE addresses Wesley W. Terpstra 2016-09-22 19:49:29 -0700
  • 972ca06729 RegField: remove RegField.bytes; it was dangerous Wesley W. Terpstra 2016-09-22 17:51:33 -0700
  • a421469754 tilelink2: change adapters to use TLAdapter(params, defaults)(node) Wesley W. Terpstra 2016-09-22 17:45:42 -0700
  • a1d5102da9 Merge pull request #323 from ucb-bar/unittest-config Howard Mao 2016-09-22 18:14:40 -0700
  • 22053289ef fix typo rv64iu -> rv64ui Howard Mao 2016-09-22 17:33:35 -0700
  • 91aab2fabc no commas in yml Henry Cook 2016-09-22 17:28:34 -0700
  • 673efb400d Merge branch 'master' into unittest-config Henry Cook 2016-09-22 16:20:53 -0700
  • 06d8140b61 Merge pull request #328 from ucb-bar/atomics Henry Cook 2016-09-22 16:20:25 -0700
  • 1e54820f8c Merge remote-tracking branch 'origin/master' into unittest-config Henry Cook 2016-09-22 16:03:51 -0700
  • 411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. Henry Cook 2016-09-22 15:59:29 -0700
  • 391be8d740 tilelink2 RegisterRouter: minLatency is never more than 1 Henry Cook 2016-09-22 15:36:13 -0700
  • a3e88fa13a tilelink2 Atomics: optimize the sign-extension circuit Wesley W. Terpstra 2016-09-22 15:13:35 -0700
  • 9f1f6fc61f Comparator: tolerate mismatched data when it is undefined Wesley W. Terpstra 2016-09-22 14:41:50 -0700
  • ed038678ef tilelink2 Fuzzer: work around for firrtl/verilator performance issue Wesley W. Terpstra 2016-09-22 11:33:40 -0700
  • 1e7480b6fc tilelink2 Monitor: work around for firrtl/verilator performance issue Wesley W. Terpstra 2016-09-22 11:02:05 -0700
  • ec2030df31 tilelink2 Legacy: convert TL1 atomic operand size Wesley W. Terpstra 2016-09-22 00:48:52 -0700
  • 0a3718881f rocketchip: re-enable testing of atomics Wesley W. Terpstra 2016-09-21 23:07:54 -0700
  • e5da3eb8bb tilelink2 Atomics: support arithmetic atomics Wesley W. Terpstra 2016-09-21 21:59:05 -0700
  • 5b80fe5b51 tilelink2 Atomics: support Logical AMOs Wesley W. Terpstra 2016-09-21 20:08:17 -0700
  • 4066fbe18f tilelink2 RAMModel: exploit latency to remove bypass Wesley W. Terpstra 2016-09-21 18:47:41 -0700
  • e0ade8c5a9 tilelink2 Atomics: exploit minLatency to eliminate bypass Wesley W. Terpstra 2016-09-21 18:03:05 -0700
  • 3bb2580223 tilelink2 Monitor: detect minLatency violations Wesley W. Terpstra 2016-09-21 18:06:39 -0700
  • 2b24c4b1b4 tilelink2: most adapters can wipe away latency Wesley W. Terpstra 2016-09-21 18:43:09 -0700
  • c115913624 tilelink2 Buffer: increase the minLatency on ports Wesley W. Terpstra 2016-09-21 18:00:57 -0700
  • 05beb20dc4 tilelink2: specify the minLatency for SRAM+RR Wesley W. Terpstra 2016-09-21 17:38:32 -0700
  • 44277c1db3 tilelink2 Parameters: include a minLatency parameter for optimization Wesley W. Terpstra 2016-09-21 17:26:52 -0700
  • cf39c32b0e tilelink2 Fuzzer: test Atomics Wesley W. Terpstra 2016-09-21 17:09:24 -0700
  • 2b9403633d tilelink2 RAMModel: support (by ignoring) atomics Wesley W. Terpstra 2016-09-21 17:08:29 -0700
  • ce204f604a tilelink2 AtomicAutomata: prototype flow control complete Wesley W. Terpstra 2016-09-20 16:49:57 -0700
  • 42b10356fa tilelink2: add a general-purpose Arbiter Wesley W. Terpstra 2016-09-21 15:28:49 -0700
  • 7636e772c8 tilelink2 Fuzzer: only generate legal atomics Wesley W. Terpstra 2016-09-21 12:35:57 -0700
  • f5d604d8f8 tilelink2 Parameters: poison ports with unsafe atomics Wesley W. Terpstra 2016-09-19 12:27:14 -0700
  • d1151e2f0f tilelink2 Nodes: split connect into eager and lazy halves Wesley W. Terpstra 2016-09-21 12:08:05 -0700
  • 684072023f tilelink2 Monitor: make it a LazyModule in the hierarchy Wesley W. Terpstra 2016-09-21 12:06:37 -0700
  • def497861b tilelink2 Bundles: add 1-way snoop bundles Wesley W. Terpstra 2016-09-21 12:04:52 -0700
  • 69a1f8cd1f tilelink2 Monitor: detect if sources are mishandled Wesley W. Terpstra 2016-09-20 19:09:48 -0700
  • 83c08a931d [WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator Henry Cook 2016-09-22 14:57:18 -0700
  • 3f3defb130 Merge pull request #329 from ucb-bar/fragmenter Wesley W. Terpstra 2016-09-22 14:42:55 -0700
  • 47c5d1a992 [WIP] Move RocketTestSuite generation into RocketchipGenerator Henry Cook 2016-09-22 14:31:45 -0700
  • d76b762657 tilelink2 Fragmenter: Mask low bits of D channel addr_lo Albert Ou 2016-09-22 12:36:28 -0700
  • cd96a66ba6 replace verilog clock divider with one written in Chisel Howard Mao 2016-09-21 20:17:32 -0700
  • cbd702e48e make sure junctions and uncore unittests both run Howard Mao 2016-09-21 18:45:12 -0700
  • 9acb352cf6 Correct Merge Conflitct -- clock, not clk (#327) mwachs5 2016-09-21 20:02:01 -0700
  • 1b1ef3be07 simplify base Coreplex bundle Yunsup Lee 2016-09-21 18:27:31 -0700
  • d2df6397cd rename trc (tile reset clock) bundles to tcr (tile clock reset) Yunsup Lee 2016-09-21 18:18:45 -0700
  • 5bb575ef74 rename internal/external MMIO network to cbus/pbus respectively Yunsup Lee 2016-09-21 18:16:04 -0700
  • 3a809b209f Allow Makefile override of RESET_DELAY (#322) mwachs5 2016-09-21 18:28:30 -0700
  • 64fe010369 [unittest] Config import tweaks Henry Cook 2016-09-21 17:40:39 -0700
  • fd5e00fed9 [coreplex] rename Testing.scala -> RocketTestSuite.scala Henry Cook 2016-09-21 17:35:39 -0700
  • 270011b768 [unittest] more Config cleanup Henry Cook 2016-09-21 17:11:57 -0700
  • 2522bdd7b8 Merge pull request #321 from ucb-bar/add-multiclock-coreplex Colin Schmidt 2016-09-21 17:23:34 -0700