riscv/rocket-chip
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rename internal/external MMIO network to cbus/pbus respectively

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This commit is contained in:
Yunsup Lee 2016-09-21 18:16:04 -07:00
parent 3a809b209f
commit 5bb575ef74
8 changed files with 25 additions and 25 deletions
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14
src/main/scala/coreplex/BaseCoreplex.scala
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@ -133,11 +133,11 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
val ioAddrMap = globalAddrMap.subMap("io")
val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
mmioNetwork.io.in.head <> mmio
val cBus = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
cBus.io.in.head <> mmio
val plic = Module(new PLIC(c.plicKey))
plic.io.tl <> mmioNetwork.port("int:plic")
plic.io.tl <> cBus.port("cbus:plic")
for (i <- 0 until io.interrupts.size) {
val gateway = Module(new LevelGateway)
gateway.io.interrupt := io.interrupts(i)
@ -145,7 +145,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
}
val debugModule = Module(new DebugModule)
debugModule.io.tl <> mmioNetwork.port("int:debug")
debugModule.io.tl <> cBus.port("cbus:debug")
debugModule.io.db <> io.debug
// connect coreplex-internal interrupts to tiles
@ -158,10 +158,10 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
tile.resetVector := io.resetVector
}
val tileSlavePorts = (0 until c.nTiles) map (i => s"int:dmem$i") filter (ioAddrMap contains _)
for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (mmioNetwork port _)))
val tileSlavePorts = (0 until c.nTiles) map (i => s"cbus:dmem$i") filter (ioAddrMap contains _)
for ((t, m) <- (uncoreTileIOs.map(_.slave).flatten) zip (tileSlavePorts map (cBus port _)))
t <> m
io.master.mmio.foreach { _ <> mmioNetwork.port("ext") }
io.master.mmio.foreach { _ <> cBus.port("pbus") }
}
}

2
src/main/scala/groundtest/BusMasterTest.scala
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@ -69,7 +69,7 @@ class BusMasterTest(implicit p: Parameters) extends GroundTest()(p)
s_req_check :: s_resp_check :: s_done :: Nil) = Enum(Bits(), 8)
val state = Reg(init = s_idle)
val busMasterBlock = addrMap("io:ext:busmaster").start >> p(CacheBlockOffsetBits)
val busMasterBlock = addrMap("io:pbus:busmaster").start >> p(CacheBlockOffsetBits)
val start_acq = Put(
client_xact_id = UInt(0),
addr_block = UInt(busMasterBlock),

2
src/main/scala/groundtest/Configs.scala
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@ -137,7 +137,7 @@ class WithComparator extends Config(
case BuildGroundTest =>
(p: Parameters) => Module(new ComparatorCore()(p))
case ComparatorKey => ComparatorParameters(
targets = Seq("mem", "io:ext:TL2:testram").map(name =>
targets = Seq("mem", "io:pbus:TL2:testram").map(name =>
site(GlobalAddrMap)(name).start.longValue),
width = 8,
operations = 1000,

2
src/main/scala/groundtest/Regression.scala
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@ -72,7 +72,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.mem.grant.ready := Bool(true)
io.cache.req.valid := !get_sent && started
io.cache.req.bits.addr := UInt(addrMap("io:ext:TL2:bootrom").start)
io.cache.req.bits.addr := UInt(addrMap("io:pbus:TL2:bootrom").start)
io.cache.req.bits.typ := UInt(log2Ceil(32 / 8))
io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0)

2
src/main/scala/rocket/dcache.scala
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@ -119,7 +119,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
require(nWays == 1)
metaWriteArb.io.out.ready := true
metaReadArb.io.out.ready := !metaWriteArb.io.out.valid
val inScratchpad = addrMap(s"io:int:dmem${tileId}").containsAddress(s1_paddr)
val inScratchpad = addrMap(s"io:cbus:dmem${tileId}").containsAddress(s1_paddr)
val hitState = Mux(inScratchpad, ClientMetadata.onReset.onHit(M_XWR), ClientMetadata.onReset)
(inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset))
} else {

8
src/main/scala/rocketchip/BaseTop.scala
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@ -65,11 +65,11 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](
val coreplex = p(BuildCoreplex)(outer.c, p)
val coreplexIO = coreplex.io
val mmioNetwork =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
val pBus =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))(
p.alterPartial({ case TLId => "L2toMMIO" })))
mmioNetwork.io.in.head <> coreplexIO.master.mmio.get
outer.legacy.module.io.legacy <> mmioNetwork.port("TL2")
pBus.io.in.head <> coreplexIO.master.mmio.get
outer.legacy.module.io.legacy <> pBus.port("TL2")
println("Generated Address Map")
for (entry <- p(GlobalAddrMap).flatten) {

4
src/main/scala/rocketchip/Periphery.scala
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@ -204,10 +204,10 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
implicit val p: Parameters
val outer: PeripheryMasterMMIO
val io: PeripheryMasterMMIOBundle
val mmioNetwork: TileLinkRecursiveInterconnect
val pBus: TileLinkRecursiveInterconnect
val mmio_ports = p(ExtMMIOPorts) map { port =>
TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost")
TileLinkWidthAdapter(pBus.port(port.name), "MMIO_Outermost")
}
val mmio_axi_start = 0

16
src/main/scala/rocketchip/Utils.scala
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@ -53,7 +53,7 @@ class GlobalVariable[T] {
object GenerateGlobalAddrMap {
def apply(p: Parameters, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
lazy val intIOAddrMap: AddrMap = {
lazy val cBusIOAddrMap: AddrMap = {
val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
@ -84,15 +84,15 @@ object GenerateGlobalAddrMap {
}.flatten
lazy val tl2AddrMap = new AddrMap(tl2Devices, collapse = true)
lazy val extIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: (p(ExtMMIOPorts) ++ pDevicesEntries), collapse = true)
lazy val pBusIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: (p(ExtMMIOPorts) ++ pDevicesEntries), collapse = true)
val memBase = 0x80000000L
val memSize = p(ExtMemSize)
Dump("MEM_BASE", memBase)
val intern = AddrMapEntry("int", intIOAddrMap)
val extern = AddrMapEntry("ext", extIOAddrMap)
val io = AddrMapEntry("io", AddrMap((intern +: (!extIOAddrMap.isEmpty).option(extern).toSeq):_*))
val cBus = AddrMapEntry("cbus", cBusIOAddrMap)
val pBus = AddrMapEntry("pbus", pBusIOAddrMap)
val io = AddrMapEntry("io", AddrMap((cBus +: (!pBusIOAddrMap.isEmpty).option(pBus).toSeq):_*))
val mem = AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))
AddrMap((io +: (p(NMemoryChannels) > 0).option(mem).toSeq):_*)
}
@ -101,8 +101,8 @@ object GenerateGlobalAddrMap {
object GenerateConfigString {
def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
val addrMap = p(GlobalAddrMap)
val plicAddr = addrMap("io:int:plic").start
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:ext:TL2:clint").start)
val plicAddr = addrMap("io:cbus:plic").start
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:pbus:TL2:clint").start)
val xLen = p(XLen)
val res = new StringBuilder
res append "plic {\n"
@ -155,7 +155,7 @@ object GenerateConfigString {
}
res append "};\n"
pDevicesEntries foreach { entry =>
val region = addrMap("io:ext:" + entry.name)
val region = addrMap("io:pbus:" + entry.name)
res append s"${entry.name} {\n"
res append s" addr 0x${region.start.toString(16)};\n"
res append s" size 0x${region.size.toString(16)}; \n"