riscv/rocket-chip
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  • 2f22fca615 rocket: reverse input edge for better output Wesley W. Terpstra 2017-04-14 16:53:40 -07:00
  • ae8fd0c60f graphML: don't draw unconnected LazyModules Wesley W. Terpstra 2017-04-14 16:35:43 -07:00
  • fcf774f125 graphML: reverse interrupt arrows Wesley W. Terpstra 2017-04-14 16:17:56 -07:00
  • d3925f0998 Add hooks to print debug information into the graphml file Jacob Chang 2017-04-14 14:21:22 -07:00
  • 153178ac4f Merge pull request #678 from ucb-bar/rammodel-atomics Wesley W. Terpstra 2017-04-14 18:08:33 -07:00
  • ba8be17c9a tilelink2: RAMModel, use CRC16 to check AMO response Wesley W. Terpstra 2017-04-14 15:00:41 -07:00
  • 6aeec673f2 util: add a CRC calculator Wesley W. Terpstra 2017-04-14 13:14:10 -07:00
  • d794218ec3 tilelink2: RAMModel now checks atomic results Wesley W. Terpstra 2017-04-13 11:41:44 -07:00
  • 4f0ae1eab7 tilelink2: annotate which test generates RAMModel output Wesley W. Terpstra 2017-04-13 11:51:10 -07:00
  • 0b65fe9532 unittest: put AtomicAutomata under regression Wesley W. Terpstra 2017-04-13 11:41:21 -07:00
  • 248acbd1b4 tilelink2: add a generic TL2 atomic evaulation unit Wesley W. Terpstra 2017-04-13 10:26:05 -07:00
  • fd7f4a4c0f jtag: make it easier to assign MFR ID externally Megan Wachs 2017-04-13 16:12:22 -07:00
  • 34d45b4fb0 Fix whitespace error Andrew Waterman 2017-04-13 17:51:19 -07:00
  • fdfcffb0b2 Catch bad physical address MSBs when VA size > PA size Andrew Waterman 2017-04-13 15:57:57 -07:00
  • 6fbbccca3e Improve Seq indexing QoR Andrew Waterman 2017-04-13 15:54:24 -07:00
  • d203c4c654 Check AMO operation legality in TLB Andrew Waterman 2017-04-12 21:49:37 -07:00
  • 6359ff96e5 Several ScratchpadSlavePort bug fixes (#676) Yunsup Lee 2017-04-14 15:25:51 +09:00
  • b9e042d2bf Unconditionally write badaddr, possibly to zero Andrew Waterman 2017-04-11 19:55:14 -07:00
  • bef88c4c30 Add pointers to package dependencies to README (#670) Megan Wachs 2017-04-11 19:54:46 -07:00
  • 907d369bde Remove tests obsoleted by new FP encoding proposal (#672) Jim Lawson 2017-04-11 19:12:35 -07:00
  • 37c9ab3459 Merge pull request #671 from ucb-bar/cork-it Wesley W. Terpstra 2017-04-11 15:55:37 -07:00
  • 1c36ab8bf7 Fragmenter: forbid multiple sink IDs Wesley W. Terpstra 2017-04-11 12:35:44 -07:00
  • 84dc2ae822 CacheCork: remove probe support Wesley W. Terpstra 2017-04-11 12:34:18 -07:00
  • 9a983c12a3 Implement new FP encoding proposal Andrew Waterman 2017-04-10 18:42:34 -07:00
  • 470c6711a7 Do some CSE by hand, per @terpstra Andrew Waterman 2017-04-10 18:40:49 -07:00
  • 71bf929505 maskgen: support wider granularity result (#665) Wesley W. Terpstra 2017-04-09 20:06:23 -07:00
  • a43bf2feae Add vectored interrupt support Andrew Waterman 2017-04-07 19:14:05 -07:00
  • 051acee76c Debug: Fix off-by-1 for detecting nonexistent harts. Megan Wachs 2017-04-07 15:22:16 -07:00
  • 01372e1686 use Wire() correctly to assign a value Megan Wachs 2017-04-07 13:58:04 -07:00
  • 9ae4838708 jtag: Get rid of chisel deprecation warnings Megan Wachs 2017-04-07 11:48:54 -07:00
  • 22c6f728c3 debug: Use flags for resume instead of program buffer. Untested. Megan Wachs 2017-04-07 09:54:51 -07:00
  • d361e9e343 debug: temporarily leave preexec in place Megan Wachs 2017-04-06 18:27:51 -07:00
  • 0e2c34b0d6 debug: update register map with new spec Megan Wachs 2017-04-06 18:00:16 -07:00
  • df5caba7bf debug: Make it easier to override parts of the Default Debug Config (#655) Megan Wachs 2017-04-06 10:33:17 -07:00
  • 5c458322b5 bump chisel for withReset bugfix Andrew Waterman 2017-04-05 19:55:57 -07:00
  • c861c4925e Don't signal access exceptions on invalid PTEs Andrew Waterman 2017-04-04 12:01:59 -07:00
  • 2e09253d26 Revive I$ parity option Andrew Waterman 2017-04-03 00:45:26 -07:00
  • 43917dd59f Get I$ s1_kill signal off the critical path Andrew Waterman 2017-04-02 22:26:40 -07:00
  • 744fb2e4b9 Cut imem.resp.ready critical path with a flow queue Andrew Waterman 2017-04-02 22:25:13 -07:00
  • 3e72f9779f Handle single-step with a pipeline stall, not a flush Andrew Waterman 2017-04-05 17:52:31 -07:00
  • c5b0b6fb85 debug: bump openOCD version to pick up read_mem fix. Use MemTest64 instead because it's more likely to fail than SimpleS0Test Megan Wachs 2017-04-04 16:49:17 -07:00
  • 2601740542 debug: fix some typos related to the ID->SEL mapping functions Megan Wachs 2017-04-04 13:43:39 -07:00
  • b94f1f15b0 debug: redirect DMI NOPs to CONTROL register so things don't hang during reset Megan Wachs 2017-04-04 13:22:51 -07:00
  • eef05cc1fc debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes. Megan Wachs 2017-04-04 11:07:33 -07:00
  • 127f121ef2 Preserve id_do_fence (#651) solomatnikov 2017-04-05 08:29:45 -07:00
  • 19f0ae64a0 Only set id_reg_fence when AMO/FENCE is actually executed Andrew Waterman 2017-04-03 16:26:57 -07:00
  • 629e9a2ef6 debug: Put DebugROM back inside the overall Debug Module (#647) Megan Wachs 2017-04-03 16:36:53 -07:00
  • d2c1bdc2ce Debug Controls (#639) Megan Wachs 2017-04-03 13:31:35 -07:00
  • 716533f77f Merge pull request #643 from ucb-bar/update-pmp-encoding Yunsup Lee 2017-03-31 20:52:49 -07:00
  • 983a561720 bump riscv-tools Yunsup Lee 2017-03-31 19:20:08 -07:00
  • 410e9cf736 I$ bugfix, to be reworked Andrew Waterman 2017-03-31 01:33:22 -07:00
  • 9f371abf3b Merge pull request #638 from ucb-bar/riscv-tools-on-priv-1.10 Henry Cook 2017-03-31 01:56:36 -07:00
  • e92eaa7156 Merge branch 'master' into riscv-tools-on-priv-1.10 Henry Cook 2017-03-30 22:31:29 -07:00
  • e8f337e963 Merge pull request #636 from ucb-bar/name-rams Henry Cook 2017-03-30 22:30:12 -07:00
  • dec567ab0c Resturn riscv-tools to the priv 1.10 branch vs the pre-merge Debug v013 version. Megan Wachs 2017-03-30 20:22:54 -07:00
  • b9550e8523 Merge branch 'master' into name-rams Henry Cook 2017-03-30 17:36:01 -07:00
  • b6da81a66c Merge pull request #624 from ucb-bar/debug_v013_pr Henry Cook 2017-03-30 17:35:26 -07:00
  • a8a2ee711c Give I$ RAMs consistent names Andrew Waterman 2017-03-30 15:50:54 -07:00
  • 2720095b8e Give D$ RAMs consistent names Andrew Waterman 2017-03-30 15:44:34 -07:00
  • 70e7e90c02 Remove splitMetadata option from L1 caches Andrew Waterman 2017-03-30 15:43:38 -07:00
  • bcaee9834c travis_wait 30 Henry Cook 2017-03-30 13:22:33 -07:00
  • 0828ebe911 debug_v013: bump fesvr to use autoexec feature for memory writes. Megan Wachs 2017-03-30 11:46:28 -07:00
  • 9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr Megan Wachs 2017-03-30 08:01:11 -07:00
  • c61714a465 Pass MODEL variable to emulator.cc Schuyler Eldridge 2017-03-29 14:27:33 -04:00
  • fd39eadcd6 New PMP encoding Andrew Waterman 2017-03-30 00:31:34 -07:00
  • 2f2b472098 rocket: split the interrupt controller into its own node Wesley W. Terpstra 2017-03-29 23:51:59 -07:00
  • a2fc51d65e soc: compatible with "simple-bus" => scanned for platform devices Wesley W. Terpstra 2017-03-29 23:50:58 -07:00
  • 9f85b2e996 Do allow make to remove .vpd files on Ctrl-C Alex Solomatnikov 2017-03-29 23:46:18 -07:00
  • 3546c8d133 If any PMPs are supported, all CSRs exist Andrew Waterman 2017-03-29 22:20:58 -07:00
  • 8f73a58d90 Report access exception, not page fault, if page-table walk fails Andrew Waterman 2017-03-29 09:49:31 -07:00
  • 25232070ec Don't redundantly set resp_ae in PTW Andrew Waterman 2017-03-29 09:48:32 -07:00
  • 80fb002962 Don't use Vec as lvalue Andrew Waterman 2017-03-29 22:04:51 -07:00
  • d3bc99e253 get local interrupts out of the tile Henry Cook 2017-03-29 19:14:04 -07:00
  • 0b9fc94421 Assertion for back-to-back uncached and cached ops (#631) solomatnikov 2017-03-29 23:07:17 -07:00
  • a14b7b5794 debug_v013: bump riscv-tools for slightly more efficient FESVR Megan Wachs 2017-03-29 21:42:36 -07:00
  • 24509fc69f debug_v013: Bump FESVR to pick up minor off-by-1 in error printing code. Megan Wachs 2017-03-29 15:20:07 -07:00
  • d8033b20fc Merge remote-tracking branch 'origin/master' into debug_v013_pr Megan Wachs 2017-03-29 14:58:04 -07:00
  • f6e72a3ef6 debug: Bump riscv-tools to pick up FESVR to version that works with debug v013 Megan Wachs 2017-03-29 14:46:01 -07:00
  • 375a039279 debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec) Megan Wachs 2017-03-28 21:14:22 -07:00
  • ca9a5a1cf7 debug: Fixes in how the SimDTM was hooked up to FESVR Megan Wachs 2017-03-28 21:13:45 -07:00
  • ff38ebdf5e debug: Bump FESVR version to initial Debug v13. Doesn't work yet. Megan Wachs 2017-03-28 21:12:57 -07:00
  • 8dfbf4532a Use 1 MHz as default timebase (#628) Andrew Waterman 2017-03-28 19:59:56 -07:00
  • 44fb3be7d0 Fix MMIO/cache refill concurrency bug in DCache Andrew Waterman 2017-03-28 16:04:02 -07:00
  • db3ed12ce3 Fix regression in groundtest DummyPTW Andrew Waterman 2017-03-27 22:58:17 -07:00
  • 4215f480ef Write instruction to badaddr on illegal instruction traps Andrew Waterman 2017-03-27 22:06:52 -07:00
  • d6ab929c41 debug: Remove older version of JTAG interface as it is superseded by the one in jtag package. Megan Wachs 2017-03-27 21:25:37 -07:00
  • cbc8d2400a debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version Megan Wachs 2017-03-27 21:24:44 -07:00
  • bb64c92906 csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again. Megan Wachs 2017-03-27 21:21:48 -07:00
  • 42ca597478 debug: Breaking change until FESVR is updated as well. Megan Wachs 2017-03-27 21:19:08 -07:00
  • 43804726ac tilelink2: more helpful requirement message Megan Wachs 2017-03-27 21:05:05 -07:00
  • 0c3d85b52b debug: add generated ROM contents and register fields. Megan Wachs 2017-03-27 21:01:36 -07:00
  • 877e1cfba1 debug: add scripts to generate v13 Debug ROM contents. Megan Wachs 2017-03-27 20:51:54 -07:00
  • ed38787c36 Merge pull request #622 from ucb-bar/priv-1.10 Wesley W. Terpstra 2017-03-27 19:28:30 -07:00
  • 05cbdced78 Work around zero-entry vec issue in Chisel Andrew Waterman 2017-03-27 17:53:48 -07:00
  • ab300f7985 Update README_TRAVIS.md Megan Wachs 2017-03-27 17:28:04 -07:00
  • 3fc74f3d08 Create README_TRAVIS.md Megan Wachs 2017-03-27 17:27:20 -07:00
  • d42d8aaea7 Make SEIP writable Andrew Waterman 2017-03-27 16:35:47 -07:00
  • c7c357e716 Add local interrupts to core (but not yet to coreplex) Andrew Waterman 2017-03-24 14:49:12 -07:00
  • 069858a20c rocket: separate page faults from physical memory access exceptions Andrew Waterman 2017-03-26 18:18:35 -07:00
  • ea0714bfcb rocket: hard-wire UXL/SXL fields to 0 Andrew Waterman 2017-03-26 21:56:35 -07:00