Andrew Waterman
f8b937d590
fix 32-bit divider bug
...
thanks, torture!
also, tidied up the code a bit.
2012-02-09 03:47:59 -08:00
Andrew Waterman
03ee49f424
fix 32-bit AMOs to upper halves of 64-bit words
...
thanks, torture!
2012-02-09 03:31:47 -08:00
Yunsup Lee
f47d888feb
vvcfgivl and vsetvl works
2012-02-09 02:35:21 -08:00
Andrew Waterman
92493ad153
fix mul/div kill bug
...
occasionally, an in-progress multiply or divide could be
erroneously killed, tying up the register forever.
2012-02-09 02:26:03 -08:00
Andrew Waterman
128ec567ed
make BTB fully associative; don't use it for JALR
...
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
2012-02-09 01:34:00 -08:00
Yunsup Lee
fcc8081c4d
hook up the vector command queue
2012-02-09 01:28:16 -08:00
Andrew Waterman
8b6b0f5367
add external memory request interface for vec unit
2012-02-08 22:30:45 -08:00
Yunsup Lee
9285a52f25
initial vu integration
2012-02-08 21:43:45 -08:00
Andrew Waterman
10b5a0006c
fix mul/div to rd=0
2012-02-08 20:11:57 -08:00
Andrew Waterman
a1855b12c2
clean up queues
2012-02-08 17:55:05 -08:00
Andrew Waterman
990e3a1b34
fix fpu port direction bug
2012-02-08 15:19:26 -08:00
Andrew Waterman
b3f6f9a5fd
fix BTB misprediction check for negative addresses
...
also index BTB with PC, not PC+4
2012-02-08 15:05:28 -08:00
Andrew Waterman
e9da2cf66a
improve id/ex datapath
...
move operand selection into decode stage; simplify bypassing
2012-02-08 06:47:26 -08:00
Andrew Waterman
d471a8b2da
arbitrate for LLFU writebacks in MEM stage
2012-02-08 04:21:05 -08:00
Andrew Waterman
ebed56500e
fix mul/wb hazard checks
...
I erroneously assumed that those instructions set id_wen.
2012-02-08 01:56:11 -08:00
Andrew Waterman
5403d069e9
add fp loads/stores
2012-02-07 23:54:25 -08:00
Christopher Celio
1be9d15944
Fixed bug regarding case sensitivity regarding ioICache,ioDCache
2012-02-07 14:07:42 -08:00
Andrew Waterman
fde8e3b696
clean up bypassing/hazard checking a bit
2012-02-06 17:26:45 -08:00
Henry Cook
41c4e10c37
Workaround for another frakking extraction error in the C backend. C and VLSI backends now both boot kernel with associativity on
2012-02-02 21:53:57 -08:00
Andrew Waterman
99a959e6b1
remove pc+4 piperegs and add new ex pc+4 adder
2012-02-02 13:33:27 -08:00
Andrew Waterman
01a156eb98
make # of dcache lines configurable
2012-02-01 21:11:45 -08:00
Andrew Waterman
b1bbf56b74
clean up wb->id bypass
2012-02-01 16:41:18 -08:00
Henry Cook
c5a4eaa0a1
Associative cache, boots kernel
2012-02-01 13:26:04 -08:00
Henry Cook
281abfbccb
New Mux1H constructor
2012-02-01 13:24:28 -08:00
Andrew Waterman
38c9105ea1
fix mul/div deadlock bug
...
If independent multiplies or independent divides were issued
back-to-back, the second wouldn't execute, causing the register
to be busy forever.
2012-01-30 21:14:28 -08:00
Andrew Waterman
bd241ea237
fix when badvaddr is set
2012-01-30 17:15:42 -08:00
Andrew Waterman
a96c92f58d
enable amomin[u]/amomax[u
2012-01-26 20:45:04 -08:00
Andrew Waterman
a7999d4525
don't flush I$ unless fence.i commits
...
otherwise, we might not make forward progress.
2012-01-26 20:37:09 -08:00
Andrew Waterman
32f5f420f3
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-01-26 20:12:42 -08:00
Andrew Waterman
41855a6d47
fix missing "otherwise" in PCR file
...
this fixes timer interrupts for VLSI backend.
2012-01-26 19:33:55 -08:00
Andrew Waterman
7172ddd050
don't flush pipeline after MFPCR
2012-01-24 18:40:08 -08:00
Andrew Waterman
97c379f1d7
made I$ associative
2012-01-24 16:51:30 -08:00
Henry Cook
aa3465699b
LFSR now a util
2012-01-24 15:26:19 -08:00
Andrew Waterman
7f26fe2c44
make icache size parameterizable
2012-01-24 15:13:49 -08:00
Henry Cook
8229d65adf
Associative cache passes asm tests and bmarks with power of 2 associativities (including 1)
2012-01-24 11:41:44 -08:00
Andrew Waterman
9e6b86fe85
Fix a nasty replay bug
...
If a mispredicted branch was followed by an instruction dependent
on a load that missed in the cache, the mispredicted path would
be executed rather than the correct path. Fail.
Example broken code:
lw x2, 0(x2) # cache miss
beq x3, x0, somewhere # mispredicted branch
move x4, x2 # wrong-path instruction dependent on load miss
2012-01-24 03:40:01 -08:00
Andrew Waterman
06fdf79dab
fix long-latency writeback arbitration bug
2012-01-24 00:56:47 -08:00
Andrew Waterman
f1c355e3cd
check pc/effective address sign extension
2012-01-24 00:15:17 -08:00
Andrew Waterman
a5a020f97b
update chisel and remove SRAM_READ_LATENCY
2012-01-23 20:59:38 -08:00
Henry Cook
8766438bb9
Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
2012-01-23 17:09:23 -08:00
Andrew Waterman
e7bf07d55e
fix AMO replay bug
2012-01-23 15:35:53 -08:00
Andrew Waterman
d59bddfbf1
fix I$ miss replay bug
2012-01-21 20:42:13 -08:00
Andrew Waterman
31c56228e2
add missing "otherwise"
2012-01-21 20:13:15 -08:00
Henry Cook
97f0852b17
DM cache with assoc-aware subunits passes all asm and bmarks
2012-01-18 17:53:26 -08:00
Henry Cook
8623d58724
split into two caches, compiles
2012-01-18 17:09:35 -08:00
Henry Cook
29ed8eb31a
More utils for nbdcache
2012-01-18 17:09:35 -08:00
Henry Cook
7e25749581
Groundwork for assoc cache implementation
2012-01-18 17:09:35 -08:00
Andrew Waterman
07f184df2f
adhere to new chisel c naming convention
2012-01-18 15:23:21 -08:00
Henry Cook
1d76255dc1
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 14:39:57 -08:00
Andrew Waterman
e4cf6391d7
fix i$ miss pathology and badvaddr bug
2012-01-17 23:47:35 -08:00
Andrew Waterman
0369b05deb
move replays to writeback stage
2012-01-17 21:12:31 -08:00
Andrew Waterman
1c8f496811
fix fpga build
2012-01-13 20:04:11 -08:00
Andrew Waterman
addfe55735
add FPGA memory generator script
2012-01-13 18:19:08 -08:00
Andrew Waterman
acf3134e80
minor control logic cleanup
2012-01-12 14:19:18 -08:00
Andrew Waterman
4807d7222b
use replay to handle I$ misses
...
this eliminates a long path in the fetch stage
2012-01-11 19:20:20 -08:00
Andrew Waterman
1a7bfd4350
remove icache req_rdy signal
2012-01-11 18:27:11 -08:00
Andrew Waterman
bcb55e581a
remove host.start signal, use reset instead
2012-01-11 17:49:32 -08:00
Andrew Waterman
92dda102b6
slight control logic cleanup
2012-01-11 16:56:40 -08:00
Andrew Waterman
938b142d64
require writes to memory to be uninterrupted
2012-01-03 18:41:53 -08:00
Andrew Waterman
142dfc6e07
made tohost/fromhost 64 bits wide
2012-01-03 15:09:08 -08:00
Andrew Waterman
20aee36c96
move PCR writes to WB stage
2012-01-02 15:42:39 -08:00
Andrew Waterman
3045b33460
remove second RF write port
...
load miss writebacks are treated like mul/div now.
2012-01-02 02:51:30 -08:00
Andrew Waterman
ffe23a1ee8
fix WAW hazard handling
2012-01-02 00:25:11 -08:00
Andrew Waterman
eb657dd250
reduce superfluous replays
...
we only replay after a cache miss if we mis-scheduled the use of a load.
2012-01-01 21:28:38 -08:00
Andrew Waterman
efc623cc36
validate BTB address and use BTB for J/JAL/JR/JALR
...
even if we weren't using the BTB for JR/JALR, we'd need to
flush the BTB on FENCE.I and on context switches, but
validating its result suffices instead.
2012-01-01 17:04:14 -08:00
Andrew Waterman
2f8fcebea0
remove datapath register resets resets
2012-01-01 16:09:40 -08:00
Andrew Waterman
f9160c53cf
fixes for correct verilog generation
2011-12-29 23:46:21 -08:00
Andrew Waterman
1028ff7d9b
fix multiplier bug
2011-12-29 23:45:09 -08:00
Andrew Waterman
d65e1a2eee
vlsi verilog compiles now but doesn't simulate
2011-12-20 22:08:27 -08:00
Andrew Waterman
38ea10a5f4
parameterized multiplier unrolling
2011-12-20 04:18:28 -08:00
Andrew Waterman
733fc8e65e
booth multiplier
2011-12-20 03:49:07 -08:00
Andrew Waterman
b5a8b6dc73
fix divider for RV32
2011-12-19 16:57:53 -08:00
Andrew Waterman
bcceb08373
add dummy mul_rdy signal
2011-12-17 07:30:47 -08:00
Andrew Waterman
96c78829b4
improve ALU and fix revealed emulator bug
2011-12-17 07:20:32 -08:00
Andrew Waterman
82700cad72
fix multiplier for rv32
2011-12-17 07:20:00 -08:00
Andrew Waterman
a8d0cd95e6
hellacache now works
2011-12-17 03:26:11 -08:00
Andrew Waterman
56c4f44c2a
hellacache returns!
...
but AMOs are unimplemented.
2011-12-12 06:49:39 -08:00
Yunsup Lee
0ea2704b80
new mftx instruction format
2011-12-12 03:23:12 -08:00
Andrew Waterman
8308345364
work in progress on hellacache
2011-12-10 07:01:47 -08:00
Andrew Waterman
ce201559f3
Support cache->cpu nacks one cycle after request
2011-12-10 00:42:09 -08:00
Andrew Waterman
c01e1f1cef
Don't replay from EX stage.
...
EX replays are now handled from MEM. We may move them to WB.
2011-12-09 19:42:58 -08:00
Andrew Waterman
218f63e66e
code cleanup/parameterization
2011-12-09 00:42:43 -08:00
Andrew Waterman
a87ad06780
Automatically infer rocketCAM address width
2011-12-06 02:05:40 -08:00
Rimas Avizienis
fa784d1d7d
made setReadLatency argument a parameter defined in consts.scala
2011-12-05 00:33:17 -08:00
Rimas Avizienis
ff95cacb55
icache/dcache tag+data arrays now implemented using Mem4()
...
however there seems to be a bug - readLatency needs to be set to 0
for C model to work, and 1 for Verilog model.
2011-12-04 01:18:38 -08:00
Rimas Avizienis
e894b79870
caches now use Mem4() memories for tag+data arrays
2011-12-03 19:41:15 -08:00
Rimas Avizienis
c580180b66
tweaks to cache/SRAM interface for TSMC65 SRAMs
2011-12-02 02:01:08 -08:00
Rimas Avizienis
e70b41241c
changed branch addr generation to get it off critical path
2011-12-02 01:56:17 -08:00
Rimas Avizienis
cf1965493b
renamed SRAM modules to match TSMC65 MC generated SRAMs
2011-12-01 13:14:33 -08:00
Rimas Avizienis
da2fdf4f85
fixed console i/o
2011-11-30 22:51:59 -08:00
Rimas Avizienis
b2894671f6
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2011-11-30 21:55:13 -08:00
Rimas Avizienis
bc44572d99
bugfixes due to new hcl jar file
2011-11-30 21:54:55 -08:00
Andrew Waterman
8f3927fdfa
queue data type is now templated
2011-11-30 18:08:26 -08:00
Rimas Avizienis
11f0e3daf4
more cleanup
2011-11-18 00:17:30 -08:00
Rimas Avizienis
c42d8149b7
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
2011-11-17 23:50:45 -08:00
Rimas Avizienis
5a322ff00c
fixed dtlb bug (swapped r/w permissions), added fake mtfsr/mffsr/fld/fst instructions
2011-11-17 11:17:37 -08:00
Rimas Avizienis
80b4253318
fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
2011-11-16 02:04:28 -08:00
Rimas Avizienis
886857fa47
writes of PC weren't being sign extended
2011-11-15 18:07:36 -08:00
Rimas Avizienis
fc0f20643a
cleanup
2011-11-15 18:06:41 -08:00
Rimas Avizienis
ae98956e6b
more amo fixes, added more options to testharness to control debug messages
2011-11-15 02:43:51 -08:00