Howard Mao
d771f37e7e
rename BusPorts to ExternalClients
2016-08-18 10:54:24 -07:00
Howard Mao
10190197c3
allow coreplex to take in more than 1 bus port
2016-08-18 10:35:25 -07:00
David Biancolin
29600f64ec
make memsize configurable
2016-08-17 16:31:34 -07:00
Andrew Waterman
ed827678ac
Write test harness in Chisel
...
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
Howard Mao
47a0c880a4
make sure TLId set in Periphery
2016-08-15 13:58:23 -07:00
Howard Mao
e939af88aa
explicitly set TLId for bus TL ports
2016-08-15 12:46:29 -07:00
Howard Mao
2c39f039b5
make external address map order overrideable
2016-08-15 11:40:28 -07:00
Howard Mao
fb476d193c
refactor main App for better code re-use
2016-08-11 16:15:23 -07:00
Howard Mao
e0ae039235
fix config string generation for extra devices
2016-08-11 10:44:32 -07:00
Howard Mao
647dbefd9b
split coreplex off into separate package
2016-08-10 18:04:22 -07:00
Howard Mao
4bfa7ceb6a
unit tests in Coreplex instead of Tile
2016-08-10 11:26:14 -07:00
Howard Mao
0ee1ce4366
separate Coreplex and TopLevel parameter traits
2016-08-10 09:49:56 -07:00
Howard Mao
f95d319162
don't use secondary external address map; collapse submap instead
2016-08-09 22:29:38 -07:00
Howard Mao
2645f74af2
clean up addrmap flatten function
2016-08-09 22:14:32 -07:00
Howard Mao
33f13d5c49
don't repeat external addr map base
2016-08-09 21:20:54 -07:00
Howard Mao
3ea2f4a6c4
refactor top-level into coreplex and platform
2016-08-09 18:26:52 -07:00
Howard Mao
dd1fed41b6
generate BootROM contents from assembly code
2016-08-05 16:39:21 -07:00
Howard Mao
9fa5b228b2
allow extra devices and top-level ports to be added without changing RocketChip.scala
2016-08-04 14:06:14 -07:00
Howard Mao
410e3e5366
make sure TraceGen gets correct addresses
2016-08-04 11:08:25 -07:00
Howard Mao
0a85e92652
Allow additional internal MMIO devices to be created without changing BaseConfig
2016-08-04 11:04:52 -07:00
Howard Mao
f04aefc95c
get rid of deprecated ZynqAdapter
2016-08-02 13:14:20 -07:00
Howard Mao
63b814fcd7
only run the important (high coverage) tests in regression suite
2016-08-02 10:54:05 -07:00
Howard Mao
b7723f1ff8
make unit tests local to the packages being tested
2016-08-01 17:02:00 -07:00
Howard Mao
98eede0505
some refactoring in RocketChip top-level
2016-08-01 17:02:00 -07:00
Megan Wachs
55c992bb3a
Use FoldRight() instead of for loop
2016-08-01 16:56:33 -07:00
Megan Wachs
8db2e8829f
Allow aggregate CONFIG on Command Line
2016-08-01 14:24:16 -07:00
Andrew Waterman
fe670e5421
Stop using deprecated FileSystemUtilities to create files
2016-07-31 18:04:56 -07:00
Andrew Waterman
058396aefe
[rocket] Implement RVC
2016-07-29 17:56:42 -07:00
Howard Mao
cb86aaa46b
fix trace generator addresses
2016-07-28 17:56:14 -07:00
Howard Mao
ecd1af326c
fix L2 deadlock bug and add more advanced trace generator
2016-07-26 12:43:08 -07:00
Howard Mao
1063d90993
make sure L1 and L2 agree on coherence policy
2016-07-25 12:20:49 -07:00
Howard Mao
6a5b2d7f59
fix assembly tests for configurations without VMU and/or user mode
2016-07-22 17:21:57 -07:00
Howard Mao
75347eed56
some fixes and cleanup to stateless bridge
2016-07-21 19:51:26 -07:00
Megan Wachs
c31c650def
If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge.
2016-07-21 13:54:28 -07:00
Howard Mao
20df74d138
generate more L1 voluntary releases in TraceGen
2016-07-21 12:33:55 -07:00
Wesley W. Terpstra
9ae23f18bd
rocket: support asynchronous external busses
2016-07-19 14:52:56 -07:00
Howard Mao
e08ec42bc0
refactor groundtest unittests into separate package
2016-07-16 23:19:55 -07:00
Megan Wachs
407bc95c42
Rename MulDivUnroll to MulUnroll
2016-07-15 15:40:17 -07:00
Megan Wachs
4c26a6bc96
Create seperate Mul/Div paramters instead of UseFastMulDiv
2016-07-15 14:40:37 -07:00
Andrew Waterman
ba08255450
bump rocket
2016-07-14 22:11:19 -07:00
Andrew Waterman
768403f8fa
Bump rocket; remove ICacheBufferWays parameter
2016-07-14 12:50:16 -07:00
Howard Mao
90bcd3dbdc
make sure DirectGroundTest testers given correct TL settings
2016-07-11 18:11:01 -07:00
Howard Mao
8f0fa11ce4
optionally export detailed status information in DirectGroundTest
2016-07-11 18:11:00 -07:00
Howard Mao
cb2a18b533
allow direct instatiation of arbitrary non-caching groundtests
2016-07-11 18:11:00 -07:00
Howard Mao
f03ffb32a0
add top that directly tests the TL -> AXI converters
2016-07-11 18:11:00 -07:00
Howard Mao
b47f8fbc41
don't use splat and bug out if too many address map entries
2016-07-11 18:10:42 -07:00
Wesley W. Terpstra
46fc9744e2
rocket: add an AXI master port into the chip
2016-07-11 12:16:44 -07:00
Wesley W. Terpstra
8ac7fa5544
ext: support multiple external AHB/AXI ports
2016-07-11 12:16:39 -07:00
Howard Mao
9ec55ebb91
don't add io:ext region to address map if no external MMIO
2016-07-08 15:29:35 -07:00
Howard Mao
35547aa428
allow NastiConverterTest and Memtest to run simultaneously
2016-07-08 13:40:52 -07:00
Howard Mao
358668699f
refactoring groundtest configuration
2016-07-08 11:40:16 -07:00
Howard Mao
eeac405ef8
get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache
2016-07-08 09:33:07 -07:00
Andrew Waterman
32ee5432dd
Fix testing of DefaultSmallConfig; bump rocket et al
2016-07-07 21:23:49 -07:00
Howard Mao
8c13e78ab5
add buffering and locking to TL -> AXI converter
2016-07-06 16:57:09 -07:00
Howard Mao
e27cb5f885
fix voluntary release issue in L2 cache
2016-07-06 16:57:01 -07:00
Howard Mao
f79a3285fb
fix TraceGen and Nasti -> TL converter
2016-07-05 17:42:57 -07:00
Howard Mao
c924ec2a22
fixing bufferless broadcast hub
2016-07-05 12:10:22 -07:00
Howard Mao
b01871c3de
test configurations for both shrinking and growing TL -> MIF
2016-07-01 18:13:33 -07:00
Howard Mao
e04e3d2571
make TestBench generator handle different top module names
2016-07-01 10:53:08 -07:00
Howard Mao
600f2da38a
export TL interface for Mem/MMIO and fix TL width adapters
2016-06-30 18:20:43 -07:00
Howard Mao
74cd588c65
refactor uncore to split into separate packages
2016-06-28 14:10:25 -07:00
Andrew Waterman
c725a78086
Merge RTC into PRCI
2016-06-27 23:08:29 -07:00
Howard Mao
d10fc84a8b
no longer require caching interfaces for groundtest tiles
2016-06-27 17:32:49 -07:00
Howard Mao
2dd8d90ae4
make Comparator fit the GroundTest model
2016-06-27 16:01:32 -07:00
Andrew Waterman
568bfa6c50
Purge legacy HTIF things
...
The SCR file is gone, too, because it was tightly coupled. The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
Andrew Waterman
2d44be747a
Fix groundtest without HTIF
2016-06-23 12:17:26 -07:00
Andrew Waterman
30331fcaeb
Remove HTIF; use debug module for testing in simulation
2016-06-23 00:32:05 -07:00
Howard Mao
4fbe7d6cf7
split the isa tests properly
2016-06-22 16:14:02 -07:00
Howard Mao
3c973d429a
rename SmallConfig to WithSmallCores
2016-06-22 16:08:27 -07:00
Howard Mao
9b9ddd0d54
get rid of leftover backup memory code
2016-06-22 16:06:41 -07:00
Howard Mao
ff43238e6e
give DualCoreConfig L2 cache to speed up test runs
2016-06-20 17:58:26 -07:00
Howard Mao
82169e971e
Dynamically compute number of L1 client channels
...
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.
This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
2016-06-20 13:02:31 -07:00
Wesley W. Terpstra
70d92995df
TestConfigs: add comparator config
2016-06-09 15:43:13 -07:00
Howard Mao
1679cf4764
fix groundtest tilelink xacts
2016-06-09 15:42:44 -07:00
Andrew Waterman
9e86b9efc9
Add provisional breakpoint support
2016-06-08 22:34:19 -07:00
Howard Mao
40ab0a7960
fix TL width adapter and make it easier to switch inner data width
2016-06-08 15:38:39 -07:00
Donggyu Kim
99b257316e
replace emulator with verilator for chisel3
2016-06-08 02:43:54 -07:00
Howard Mao
2cd897e240
Revert "include the unmatched field in CDEMatchError"
...
This reverts commit ff2937a788
2016-06-07 16:13:01 -07:00
Howard Mao
8db27a36c4
fix Tile reset power on behavior
2016-06-07 11:06:38 -07:00
Wesley W. Terpstra
5495705acf
Configs: enable AHB for FPGAs
2016-06-06 21:36:09 -07:00
Wesley W. Terpstra
ef27cc3a33
RocketChip: handle atomics only if needed
2016-06-06 21:36:03 -07:00
Wesley W. Terpstra
3e0ec855cf
RocketChip: add ahb mem interface
2016-06-06 21:35:59 -07:00
Wesley W. Terpstra
d2b505f2d2
RocketChip: rename mem to mem_axi in preparation for new bus type
2016-06-06 21:35:55 -07:00
Wesley W. Terpstra
2086c0d603
Configs: add a parameter to control the memory subsystem interface
2016-06-06 21:35:43 -07:00
Wesley W. Terpstra
2ddada1732
ahb: add mmio_ahb option
2016-06-06 21:35:39 -07:00
Wesley W. Terpstra
31f1dcaf84
ahb: rename mmio outputs to mmio_axi
2016-06-06 21:35:34 -07:00
Wesley W. Terpstra
7a24527448
ahb: make MMIO channels specifiy bus type (we will have more than one bridge)
2016-06-06 21:35:30 -07:00
Wesley W. Terpstra
f3a557b67b
ahb: AHB parameters should be site specific
...
Conflicts:
src/main/scala/Configs.scala
2016-06-06 21:35:24 -07:00
Howard Mao
ff2937a788
include the unmatched field in CDEMatchError
2016-06-06 11:23:20 -07:00
Andrew Waterman
d24c87f8ba
Update PLIC/PRCI address map ( #124 )
2016-06-06 04:51:55 -07:00
Andrew Waterman
ece3ab9c3d
Refactor AddrMap and its usage ( #122 )
2016-06-03 17:29:05 -07:00
Andrew Waterman
c8338ad809
Instantiate Debug Module ( #119 )
2016-06-02 10:53:41 -07:00
Andrew Waterman
44a216038f
Use more generic TileLinkWidthAdapter
2016-05-27 13:38:13 -07:00
Andrew Waterman
10f0e13c25
Use more parsimonious queue depths
2016-05-26 18:04:22 -07:00
Andrew Waterman
3cc236e9c4
By default, use same TileLink width everywhere
...
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
2016-05-26 18:04:01 -07:00
Wesley W. Terpstra
976d4d3184
ahb: AHB parameters should match TileLink parameters by default
...
Closes #116
2016-05-25 18:01:25 -07:00
Andrew Waterman
ec0d178010
Support M-mode-only implementations
2016-05-25 15:40:53 -07:00
Andrew Waterman
e82c080c3c
Add blocking D$
2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5
remove zscale
2016-05-19 09:43:15 -07:00
Colin Schmidt
abb0e2921b
return non-zero exit codes when an assertion fires
...
This ensures that assertion failures, which currently print a message to
the console but return a successful exit code, now will cause non-zero
exit code. This is meant to help automated tools like travis and
buildbot do a better job at catching assertions.
This impacts the various run-* targets in the simulation
directories.
2016-05-18 12:57:58 -07:00
