riscv/rocket-chip
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Author SHA1 Message Date
Henry Cook
efe7165b54 tile: BaseTile refactor, pt 2 
* 2 layer cake
* no more bundle traits, only call to IO
 2018-01-02 15:37:31 -08:00
Henry Cook
1579ddb97e tile: removed RocketTileWrapper. RocketTile now HasCrossing. 2017-12-28 14:00:13 -08:00
Henry Cook
1cd018546c tile: BaseTile refactor, pt 1 
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
 2017-12-26 11:04:15 -08:00
Henry Cook
ba6dd160a3 diplomacy: allow access to sram Device info 2017-12-22 19:00:43 -08:00
Henry Cook
d9c5ec4f7b coreplex: HasTiles supplies def tileParams 2017-12-20 17:18:55 -08:00
Henry Cook
ddaeedf2d0 coreplex: make HasTiles more generic 
HasTiles now deals with only extremely general tile IOs.
Some RocketTiles specific behavior moved into RocketCoreplex.
BaseTile now has optional LocalInterruptNode.
 2017-12-20 17:18:55 -08:00
Henry Cook
9b82f1098d
Merge pull request #1154 from freechipsproject/bump-sbt 
Bump chisel, firrtl, and sbt
 2017-12-19 14:16:47 -08:00
Henry Cook
895c4b9261
Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144)" (#1162) 
This reverts commit a542ae687e.
 2017-12-19 12:16:26 -08:00
Megan Wachs
74d9326ebc
JTAG: Revert to Chisel._ for Issue 1160 (#1161) 
* JTAG: Revert to Chisel._ for Issue 1160

* JTAG: Revert to Chisel._ for Issue 1160

* jtag: revert everything to Chisel._

* jtag: Revert all modules to Chisel._ vs chisel3, due to FIRRTL issues with chisel3 generated code
 2017-12-18 21:02:31 -08:00
Henry Cook
a31ba2ea2e
diplomacy: LazyModule factory uses ValName (#1159) 
* diplomacy: LazyModule factory uses ValName
 2017-12-18 15:40:30 -08:00
Jack Koenig
3df401eef7 Bump chisel3 and firrtl and bump sbt to version 1.0.4 
sbt bump must be accompanied by bump to chisel3 and firrtl using sbt
1.0.4
 2017-12-18 12:09:21 -08:00
Jack Koenig
b914564a62 Move build.scala -> build.sbt 2017-12-18 12:08:51 -08:00
Jim Lawson
0b2d200e91 Bump scala and sbt-site plugin versions. 2017-12-18 12:08:33 -08:00
Jacob Chang
09160d0cd5
Changed label for DCache and ICache error covers + take away exclusio… (#1155) 
* Changed label for DCache and ICache error covers + take away exclusion that shouldn't be there

* rocket: add d-channel error to I$
 2017-12-13 20:16:36 -08:00
Wesley W. Terpstra
a542ae687e
ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144) 2017-12-08 17:35:14 -08:00
Wesley W. Terpstra
c2a0319dc4
Merge pull request #1151 from freechipsproject/error-atoms 
Error atomics
 2017-12-08 17:34:55 -08:00
Wesley W. Terpstra
efc793d52e CloneModule: must be public to be used in pattern matches 2017-12-08 14:57:08 -08:00
Wesley W. Terpstra
2ca03384ec diplomacy: skip anonymous class names 2017-12-08 14:36:12 -08:00
Jack Koenig
588dacec17
Bump Chisel and Firrtl (#1134) 2017-12-08 14:22:18 -08:00
Wesley W. Terpstra
18b8a61775 Error device: require explicit control of atomic and transfer sizes 2017-12-08 13:41:09 -08:00
Wesley W. Terpstra
6a0150aad7 Error device: mark executable to support testing erroneous I$ refill 2017-12-08 12:38:06 -08:00
Gleb Gagarin
9cc37b8444
Merge pull request #1150 from freechipsproject/fix-uncached-unaligned-fetch 
Prevent frontend deadlock fetching from uncacheable memory
 2017-12-08 11:02:44 -08:00
Andrew Waterman
676110bc1f Add cover for a1ebe6da4d 2017-12-07 21:03:42 -08:00
Andrew Waterman
a1ebe6da4d Prevent frontend deadlock fetching from uncacheable memory 
After detecting a corrupted BTB, don't speculatively update it until
the next non-speculative fetch.  This prevents the frontend from replaying
forever.
 2017-12-07 18:56:06 -08:00
Jacob Chang
ec3789b365
Add Cross Cover Property Library (#1149) 
Add cover points related to memory error to I/D Cache
 2017-12-07 18:46:10 -08:00
Andrew Waterman
5c204f98d5
When writing full words to ITIM, ECC errors are correctable (#1148) 
* When writing full words to ITIM, ECC errors are correctable

* Disable D$ tag reset state machine when using scratchpad
 2017-12-07 16:00:26 -08:00
Richard Xia
cfa819fc58
Merge pull request #1142 from freechipsproject/fix-typo-in-cover-property-name 
Fix typo in breakpoint cover property.
 2017-12-04 15:10:05 -08:00
Richard Xia
50de991f18 Fix typo in breakpoint cover property. 2017-12-04 14:04:24 -08:00
Wesley W. Terpstra
b8098d18be
diplomacy: remove the :=? operator in favour of magic :*=* (#1139) 
The reason for the :=? operator was for when you have an adapter chain
whose direction of cardinality you could not know. We used explicit
directives to tell these compositions which way to go.

Unfortunately, that makes the API leaky. You think the chain of adapters
is just one adapter, but you have to use strange Cardinality scopes to
use it. That's just bad.

The new :*=* just automagically figures it out from the graph.
 2017-12-01 18:28:37 -08:00
Wesley W. Terpstra
dedf396915
groundtest: connect the ibus to a fictitious master (#1140) 2017-12-01 18:28:24 -08:00
Henry Cook
71ddd797bf
Merge pull request #1138 from freechipsproject/cover_tag_ecc_error_during_fence_i 
Added coverage point to cover the case when ECC error happens during …
 2017-12-01 18:00:11 -08:00
Gleb Gagarin
7c2df9f0bf Cover the case when there is an ECC error in DCache data array during fence.i execution 2017-12-01 16:28:28 -08:00
Gleb Gagarin
74bd61c556 Added coverage point to cover the case when ECC error happens during fence.i execution 2017-12-01 15:50:31 -08:00
Wesley W. Terpstra
4bac8be483
Merge pull request #1094 from freechipsproject/in-situ-unit-tests 
In situ unit tests
 2017-12-01 13:27:30 -08:00
Wesley W. Terpstra
8781d2b2e7 diplomacy: provide a val name for all LazyModule constructions 2017-12-01 11:28:21 -08:00
Wesley W. Terpstra
a3e44375c6 ValName: 'lazy val' now also counts for providing a name 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
fe8d557751 PeripheryBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
93c8010aca FrontBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
e489c4226e diplomacy: remove node arity and allow empty Nexus nodes (Xbars) 
This removes the mostly obsolete 'numIn/Out' range restrictions on nodes.
It also makes it possible to connect optional crossbars that disappear.

val x = TLXbar()
x := master
slave := x

val y = TLXbar()
x :=* y // only connect y if it gets used

This will create crossbar x, but crossbar y will disappear.
 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
6a25a3b7ac tilelink: we can have helper objects for terminal nodes now too! 
The new rule is you should have an object.apply method if you only have a
single .node.
 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
2092cb4ec8 diplomacy: reprotect Node bundles after module construction is completed 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
fdeed7bbb3 unittest: add an API for describing LazyModule unit tests 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
cc789e9063 diplomacy: protect more of the unstable API 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
8ed9e78903 diplomacy: support cloning of LazyModules 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
b43bcdfcd1 CloneModule: beat chisel into submission 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
1f23f9f865 diplomacy: categorize parameter resolution by direction+side 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
fbbfc9c096 diplomacy: include edge type in inward/outward node handles 
This is necessary capture the node implementation in the handle,
which is in turn necessary to support cloning a Node.
 2017-12-01 11:26:58 -08:00
Wesley W. Terpstra
ea03f71f97
Merge pull request #1135 from freechipsproject/decoupled-loop-fix 
TileLink compliance: d_bits may not depend on d_ready
 2017-11-30 18:21:37 -08:00
Wesley W. Terpstra
35506279af regmapper: fix d_ready => d_bits loop in RegField.bytes 
RegField.bytes updates only those bytes which are written every cycle.
However, there was a bug that it would try to return the updated value on reads.
This led to another TL-spec violating combinational path, just like the Debug module.
 2017-11-30 16:38:45 -08:00
Wesley W. Terpstra
fc1f5be316 Debug: fix a latent combinational loop (d_ready => d_bits) 
When passed a Wire, WNotify outputs that wire on reads wire => d_bits.
Furthermore, it updates the Wire when a write occures d_ready => wire.

These registers should be returning undefined value on read, anyway.
 2017-11-30 16:36:45 -08:00