Rimas Avizienis
|
c42d8149b7
|
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
|
2011-11-17 23:50:45 -08:00 |
|
Rimas Avizienis
|
80b4253318
|
fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
|
2011-11-16 02:04:28 -08:00 |
|
Rimas Avizienis
|
886857fa47
|
writes of PC weren't being sign extended
|
2011-11-15 18:07:36 -08:00 |
|
Rimas Avizienis
|
48cec01710
|
updated riscv-bmarks and riscv-tests to build with new toolchain
|
2011-11-15 00:11:22 -08:00 |
|
Rimas Avizienis
|
cd6e463320
|
added ei and di instructions
|
2011-11-14 13:48:49 -08:00 |
|
Rimas Avizienis
|
b791010bb1
|
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
|
2011-11-14 04:13:13 -08:00 |
|
Rimas Avizienis
|
890bfa7c48
|
added IPIs and timer interrupts
|
2011-11-14 03:24:02 -08:00 |
|
Rimas Avizienis
|
5b29765917
|
synced up with supervisor mode state in latest ISA simulator
|
2011-11-14 01:37:20 -08:00 |
|
Rimas Avizienis
|
44419511b7
|
timer interrupt fixes
|
2011-11-13 00:32:08 -08:00 |
|
Rimas Avizienis
|
f86d5b1334
|
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
|
2011-11-10 11:26:13 -08:00 |
|
Rimas Avizienis
|
4bd0263a4a
|
added misaligned instruction check, cleaned up badvaddr handling
|
2011-11-10 03:38:59 -08:00 |
|
Rimas Avizienis
|
603ede8bfe
|
access faults now write badvaddr PCR register with faulting address
|
2011-11-10 02:46:09 -08:00 |
|
Rimas Avizienis
|
36aa4bcc9d
|
moved exception handling from ex stage in dpath to mem stage in ctrl
|
2011-11-10 02:26:26 -08:00 |
|
Rimas Avizienis
|
62407b4668
|
more tlb/ptw fixes
|
2011-11-10 00:23:29 -08:00 |
|
Rimas Avizienis
|
6664af3bc0
|
cleanup before adding dtlb
|
2011-11-09 23:27:29 -08:00 |
|
Rimas Avizienis
|
9aca403aa8
|
more itlb integration & cleanup
|
2011-11-09 23:18:14 -08:00 |
|
Rimas Avizienis
|
c29d2821b4
|
cleanup, fixes, initial commit for dtlb.scala
|
2011-11-09 21:54:11 -08:00 |
|
Rimas Avizienis
|
e96430d862
|
integrating ITLB & PTW
|
2011-11-09 14:52:17 -08:00 |
|
Rimas Avizienis
|
7130edac8d
|
fix for flushed div/mul instructions
|
2011-11-07 01:03:47 -08:00 |
|
Rimas Avizienis
|
4d64099103
|
cleanup
|
2011-11-04 20:52:21 -07:00 |
|
Rimas Avizienis
|
4459935554
|
dcache fixes - all tests and ubmarks pass, hello world still broken
|
2011-11-04 15:40:41 -07:00 |
|
Rimas Avizienis
|
3a02028a35
|
fixes to exception and dcache miss/blocked handling
|
2011-11-02 13:32:32 -07:00 |
|
Rimas Avizienis
|
7a528d6255
|
fixes for div/mul hazard checking + cleanup
|
2011-11-01 23:14:34 -07:00 |
|
Rimas Avizienis
|
d8ffecf565
|
dcache fix
|
2011-11-01 22:10:06 -07:00 |
|
Rimas Avizienis
|
7479e085ec
|
dcache loads working - 1/2 cycle load/use delay depending on load type
|
2011-11-01 22:04:45 -07:00 |
|
Rimas Avizienis
|
3b3d988fde
|
dcache loads working - 1/2 cycle load/use delay depending on load type
|
2011-11-01 21:25:52 -07:00 |
|
Rimas Avizienis
|
2b67eee683
|
pipeline changes for replay on dcache miss
|
2011-11-01 19:05:27 -07:00 |
|
Rimas Avizienis
|
08b89e7710
|
interface cleanup, major pipeline changes
|
2011-11-01 17:59:27 -07:00 |
|
Rimas Avizienis
|
c06e2d16e4
|
initial commit of rocket chisel project, riscv assembly tests and benchmarks
|
2011-10-25 23:02:47 -07:00 |
|