Yunsup Lee
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e53792a1eb
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fix bug in rocket's vector datapath related to wakeup
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2012-02-23 10:14:14 -08:00 |
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Andrew Waterman
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7c929afe2b
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HTIF now controls CPU reset
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2012-02-22 19:30:03 -08:00 |
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Andrew Waterman
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3eebf40310
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nack CPU requests during any replay
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2012-02-22 18:37:13 -08:00 |
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Henry Cook
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62837537f4
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Improved TileIO organization, beginnings of hub implementation
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2012-02-22 18:24:52 -08:00 |
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Henry Cook
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24a32c2811
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Refining tilelink interface
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2012-02-22 12:15:47 -08:00 |
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Henry Cook
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18bd0c232b
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Added coherence message type enums
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2012-02-22 12:15:47 -08:00 |
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Daiwei Li
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22f8dd0994
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Hook up resp_type to vector unit
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2012-02-21 18:20:32 -08:00 |
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Andrew Waterman
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cfd79c731b
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add resp_type to ext_mem interface
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2012-02-21 17:42:00 -08:00 |
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Andrew Waterman
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9a80adef50
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only instantiate VI$ if HAVE_VEC
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2012-02-21 15:53:19 -08:00 |
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Andrew Waterman
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c8f768c8b3
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fix AMO replay bug
like the recent AMO bug fix, but affects stores too. oops.
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2012-02-21 14:39:54 -08:00 |
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Andrew Waterman
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d5608b2728
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fix AMO replay bug
didn't check for structural hazard on AMO unit
if a replay was initiated one cycle before before
a hit-under-miss AMO was issued
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2012-02-21 01:02:16 -08:00 |
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Andrew Waterman
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6135615104
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unify cache backend interfaces; generify arbiter
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2012-02-20 00:51:48 -08:00 |
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Andrew Waterman
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7034c9be65
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new htif protocol and implementation
You must update your fesvr and isasim!
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2012-02-19 23:15:45 -08:00 |
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Andrew Waterman
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9af86633d7
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invalidate I$ prefetcher when invalidating I$
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2012-02-17 17:56:01 -08:00 |
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Henry Cook
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e555fd3fc4
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Abstract class for coherence policies
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2012-02-16 12:59:38 -08:00 |
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Henry Cook
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d46e59a16d
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Abstract base nbcache class
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2012-02-16 12:34:51 -08:00 |
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Henry Cook
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124efe5281
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Replace nbcache manipulation of meta state bits with abstracted functions
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2012-02-16 10:43:40 -08:00 |
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Henry Cook
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619929eba1
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Added coherence tile function defs, with traits and constants
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2012-02-16 00:16:45 -08:00 |
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Andrew Waterman
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1b5e39e7fc
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fix bug in BTB
a BTB update followed by a taken branch could cause incorrect control flow.
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2012-02-15 21:36:08 -08:00 |
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Andrew Waterman
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fc5ba769da
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disable vector unit by default
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2012-02-15 18:58:41 -08:00 |
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Andrew Waterman
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8b3b3abd3d
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fix external memory request nack logic
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2012-02-15 18:57:40 -08:00 |
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Andrew Waterman
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fe2c1d1321
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add vec->ctrl fences
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2012-02-15 18:31:19 -08:00 |
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Yunsup Lee
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82cd3625c2
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add in vackq interface
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2012-02-15 17:53:24 -08:00 |
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Andrew Waterman
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c13524ad3a
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fix vcmdq full replay logic
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2012-02-15 17:49:12 -08:00 |
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Yunsup Lee
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258d050e1b
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add stall logic for vector command queues
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2012-02-15 14:48:41 -08:00 |
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Yunsup Lee
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32bdf5098a
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refactor vector control logic & datapath in the rocket core
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2012-02-15 13:30:22 -08:00 |
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Yunsup Lee
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7c11c1406c
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vector-vector add working!
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2012-02-15 02:28:07 -08:00 |
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Yunsup Lee
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6bdf9dc513
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hwacha integration: now it compiles correctly!
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2012-02-14 23:34:57 -08:00 |
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Yunsup Lee
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a51c7cc927
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new build system with updated chisel, hwacha
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2012-02-14 19:43:59 -08:00 |
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Andrew Waterman
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0ec7767c13
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declaring success on FPU for now
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2012-02-14 19:11:57 -08:00 |
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Andrew Waterman
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297223a13c
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squash subsequent external mem request after nack
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2012-02-14 15:12:16 -08:00 |
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Andrew Waterman
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38c67e5a9e
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add fmin.[s|d] and fmax.[s|d]
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2012-02-14 06:37:18 -08:00 |
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Andrew Waterman
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ee9fc10668
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add fcvt.s.d, fcvt.d.s
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2012-02-14 06:03:43 -08:00 |
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Andrew Waterman
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ce202c73d1
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add fsgnj[n|x].[s|d]
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2012-02-14 04:24:35 -08:00 |
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Andrew Waterman
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1d604bcd49
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remove top-level Makefile
new, simpler build instructions are in the README.
note that for "make run-asm-tests-debug" you need to update your fesvr.
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2012-02-14 02:53:43 -08:00 |
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Andrew Waterman
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15dc2d8c40
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add fp writeback arbitration logic
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2012-02-14 00:32:25 -08:00 |
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Henry Cook
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0671a99712
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NBcache works with associativities other than powers of 2
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2012-02-13 21:44:32 -08:00 |
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Henry Cook
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6d36168183
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Fixed two associative nbcache bugs, one in amo replays and one in the flush unit
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2012-02-13 21:44:32 -08:00 |
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Andrew Waterman
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0366465cb1
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parameterize the scoreboards
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2012-02-13 18:12:23 -08:00 |
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Andrew Waterman
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6c2d8a37ae
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remove a partial update that makes chisel barf
chisel regards it as a combinational loop, even though it isn't.
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2012-02-13 16:45:29 -08:00 |
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Andrew Waterman
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c78c738f60
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minor cleanups
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2012-02-13 03:13:49 -08:00 |
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Andrew Waterman
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b5a19a54a3
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add fcvt.[s|d].[w|l][u]
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2012-02-13 02:01:26 -08:00 |
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Andrew Waterman
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a4a9d2312c
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add fcvt.[w|l][u].[s|d], f[eq|lt|le].[s|d]
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2012-02-13 01:30:01 -08:00 |
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Andrew Waterman
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069037ff3a
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add FP recoding
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2012-02-12 23:31:50 -08:00 |
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Andrew Waterman
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25ecfb9bbc
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clean up caches
- remove incompatible blocking D$
- remove direct-mapped nonblocking cache
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2012-02-12 20:32:06 -08:00 |
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Andrew Waterman
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08b6517a23
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add FP ops mftx, mxtf, mtfsr, mffsr
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2012-02-12 20:12:53 -08:00 |
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Andrew Waterman
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9bb1558a34
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WIP on FPU
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2012-02-12 04:36:01 -08:00 |
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Andrew Waterman
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50a283d311
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move store data generation into EX stage
doing so removes it from the critical path of FP store unrecoding.
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2012-02-12 01:35:55 -08:00 |
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Andrew Waterman
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725190d0ee
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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Andrew Waterman
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f8b937d590
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fix 32-bit divider bug
thanks, torture!
also, tidied up the code a bit.
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2012-02-09 03:47:59 -08:00 |
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