riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,530 Commits 1 Branch 0 Tags
dbc5e7c49460f99259f89fc11d979b906a307a4a
Commit Graph

540 Commits

Author SHA1 Message Date
Wesley W. Terpstra
b99662796d PLIC: converted to TL2 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
bddfa4d69b Debug: make address configurable 2016-10-31 11:42:13 -07:00
Megan Wachs
10d084b9f3 DebugModule: Use the power of RegisterRouter to simplify the DebugROM code. 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
650f6fb23f diplomacy: add BlindNodes for use as external ports 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0edcd3304a diplomacy Nodes: leave flipping to the MixedNode implementation 2016-10-31 11:41:18 -07:00
Megan Wachs
d530ef7236 DebugModule: translate to TL2 with {32,64}-bit XLen width 2016-10-31 11:41:18 -07:00
Howard Mao
f0e9a2a081 Fix PutBlock after Release bug 
There is logic in the broadcast hub to skip the outer acquire if there
is an outgoing release, since the data will be written out through the
release channel. However, this will cause an issue in the case of
PutBlock requests. If the tail beats of the PutBlock show up after the
outer release has already been sent, the data will be corrupted.

The fix is to make the outer release block if there are pending
inner PutBlock beats.
 2016-10-28 18:26:34 -07:00
Andrew Waterman
e45b41b4b6 Don't rely on SeqMem output after read-enable is low 2016-10-27 23:44:10 -07:00
Howard Mao
900a7bbcf1 add PutAtomic support to width adapter 2016-10-26 09:58:26 -07:00
Wesley W. Terpstra
fee67c4abf diplomacy: add methods to find {out,in}ner-most common node 2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
67ab27f5a5 diplomacy: guess the LazyModule name from the containing class 2016-10-25 15:58:09 -07:00
Wesley W. Terpstra
4d50733548 tilelink2 ToAXI4: use helper method for a_last (#418) 2016-10-25 10:16:42 -07:00
Wesley W. Terpstra
a5ac106bb8 axi4 ToTL: fix decode error arbitration (#417) 
When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.

This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
 2016-10-24 22:15:19 -07:00
Wesley W. Terpstra
4c815f7958 tilelink2 Parameters: fix {contains,supports}Safe (#416) 
When there is only one manager, you still want to know if the address
was wrong on the link to that manager!
 2016-10-24 20:37:04 -07:00
Wesley W. Terpstra
8bfd6bcd4d axi4: ensure we accept AR before reporting R (#411) 2016-10-21 21:02:05 -07:00
Wesley W. Terpstra
7c334e3c34 axi4 ToTL: shorter critical path on Q.bits if errors go first 2016-10-17 01:00:49 -07:00
Wesley W. Terpstra
73010c79a3 axi4 ToTL: handle bad AXI addresses 2016-10-17 00:12:26 -07:00
Wesley W. Terpstra
501d6d689f axi4: Test ToTL 2016-10-16 22:04:06 -07:00
Wesley W. Terpstra
5a1da63b5a axi4: prototype ToTL adapter 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
72e5a97d40 tilelink2: factor out the OH1ToOH function 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
d09f43c32f axi4 Bundles: add a size calculation helper 
The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
20288729b9 tilelink2 Isolation: cross the valid signals as well 
Refactor the code to be less copy-pasty
 2016-10-14 18:28:36 -07:00
Wesley W. Terpstra
ac0bb841da AsyncQueue: cope with far reset propagation delay 2016-10-14 18:05:35 -07:00
Wesley W. Terpstra
8f3c2ddfc3 tilelink2 Crossing: these asserts should be done by the AsyncQueue 2016-10-14 16:54:09 -07:00
Wesley W. Terpstra
a82cfb8306 tilelink2: replace addr_hi with address (#397) 
When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
 2016-10-14 14:09:39 -07:00
Wesley W. Terpstra
54b73aef57 tilelink2: WidthWidget and Fragmenter no longer erase latency 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
200cf3dd13 tilelink2 Nodes: include some options to test for conformance 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
5d5b5a66f4 tilelink2 RAMModel: fix a write-bad-data bug 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e5a1483358 tilelink2 Fragmenter: eliminate most of the registers on A 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
99c7003d11 tilelink2: allow preemption of Fragmenter and WidthWidget 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b42cfdc9dd tilelink2 Arbiter: there is only one winner 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b6e9b0c558 tilelink2 Arbiter: allow preemption of first beat 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0aebf9e341 tilelink2 ToAXI4: no arbitration path register needed 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0e897b905f tilelink2 RegisterRouter: data path register is no longer required 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
c4eadd3ab3 tilelink2 Monitor: enforce stricter transaction ordering 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
d8a1163131 tilelink2 Monitor: don't enforce Irrevocable any more 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
405f66da32 tilelink2 WidthWidget: cope with Decoupled inputs 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e2e72ac979 tilelink2 Fragmenter: cope with Decoupled input 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
023c6402e9 tilelink2: switch to DecoupledIO syntax 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
4c1c52486b axi4 Fragmenter: handle more inflight AXI requests than we have space 2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
8005266131 axi4 Fragmenter: refine sideband FSM for case of last fragment 2016-10-13 15:52:32 -07:00
Wesley W. Terpstra
19064e602b axi4 Fragmenter: align all output accesses 
We promised the output is aligned. Make good on that!
 2016-10-13 15:52:27 -07:00
Wesley W. Terpstra
84be93f9f3 axi4 Fragmenter: confirm correct handling of last 2016-10-13 14:01:23 -07:00
Wesley W. Terpstra
1c79a23a8b axi4 Fragmenter: initialize error response to 0 2016-10-13 13:46:24 -07:00
Wesley W. Terpstra
958af132ba axi4 Fragmenter: optimize dynamic slave lookup 2016-10-12 17:29:38 -07:00
Wesley W. Terpstra
11169d155c axi4: add a Buffer to put between nodes 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a9a3f7dd4e tilelink2 RAMModel: include name of test in output 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
345eefd81b axi4: include unit tests 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a6c6d99848 axi4: prototype Fragmenter 2016-10-12 17:08:49 -07:00
Wesley W. Terpstra
c918aa6d89 axi4: name AdapterNode parameters properly 2016-10-12 17:02:02 -07:00