Logo
Explore Help
Sign In
riscv/rocket-chip
Watch 1
Star 0
Fork 0
Code Releases Activity
Files
7c334e3c34ff89ea6a86c7ef08a4babdda44bf45
rocket-chip/src/main/scala/uncore
T
History
Wesley W. Terpstra 7c334e3c34 axi4 ToTL: shorter critical path on Q.bits if errors go first
2016-10-17 01:00:49 -07:00
..
agents
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
axi4
axi4 ToTL: shorter critical path on Q.bits if errors go first
2016-10-17 01:00:49 -07:00
coherence
Move a bunch more things into util package
2016-09-29 14:23:42 -07:00
converters
TileLink utility objects should not take implicit parameters
2016-09-26 17:28:21 -07:00
devices
tilelink2: replace addr_hi with address (#397)
2016-10-14 14:09:39 -07:00
tilelink
Use <> instead of := for bi-directional connections
2016-10-04 22:29:39 -07:00
tilelink2
tilelink2: factor out the OH1ToOH function
2016-10-16 22:04:01 -07:00
util
Move a bunch more things into util package
2016-09-29 14:23:42 -07:00
Builder.scala
Use CDEMatchError for improved performance (#304)
2016-09-15 19:47:18 -07:00
Consts.scala
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00
Package.scala
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00
Powered by Gitea Version: 1.27.1 Page: 13ms Template: 5ms
Dark
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API