Andrew Waterman
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c6bcc832a1
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Chisel3: Don't use Vec.fill for IOs
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2015-09-20 13:43:56 -07:00 |
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Christopher Celio
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c9d89226fb
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Generated *.d file of tests now kept in order
-Changed Set to LinkedHashSet in Testing.scala
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2015-09-11 18:36:04 -07:00 |
|
Andrew Waterman
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700910adff
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Chisel3 compatibility fix for <>
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2015-08-05 15:34:40 -07:00 |
|
Andrew Waterman
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34b9a7fdc5
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Various Chisel3 compatibility changes
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2015-08-03 18:54:56 -07:00 |
|
Henry Cook
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0c9a7817b6
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Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7)
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2015-07-30 16:30:00 -07:00 |
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Henry Cook
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51c42083d0
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Add new junctions repo as submodule (contains externally facing buses and peripherals).
Bump all submodules.
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2015-07-29 18:15:45 -07:00 |
|
Henry Cook
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d21ffa4dba
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Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
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2015-07-28 00:24:07 -07:00 |
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Yunsup Lee
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efd6458a3d
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add zscale programs
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2015-07-27 19:06:06 -07:00 |
|
Henry Cook
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bd4ff35a4b
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Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS
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2015-07-22 11:49:10 -07:00 |
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Yunsup Lee
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a99b1e3a01
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append config name to generated Makefrag filename
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2015-07-17 12:34:49 -07:00 |
|
Yunsup Lee
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e7802825c3
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add Zscale testing
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2015-07-17 12:02:02 -07:00 |
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Yunsup Lee
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4c7c3f5bb2
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add test generate for ZscaleTop
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2015-07-14 16:26:28 -07:00 |
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Henry Cook
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76046c52fe
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Cleanup testing rv64uf
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2015-07-13 18:58:58 -07:00 |
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Henry Cook
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302cd3e638
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Added BuildZscale param for use in Top and makefrag generation
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2015-07-13 15:46:42 -07:00 |
|
Henry Cook
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407d8e473e
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first cut at parameter-based testing
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2015-07-13 14:54:26 -07:00 |
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Henry Cook
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4e4015089d
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rename Configs source
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2015-07-09 15:04:11 -07:00 |
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Yunsup Lee
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09e29e8fe0
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add zscale
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
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2015-07-07 20:38:47 -07:00 |
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Yunsup Lee
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e6a13cdeba
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New machine-mode timer facility
Mirroring Andrew's commit to reference-chip
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2015-07-07 17:26:07 -07:00 |
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Henry Cook
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4fbb0f80ff
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Added some multicore/multibanks named ChiselConfigs
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2015-07-06 18:21:06 -07:00 |
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Henry Cook
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d3ccec1044
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Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
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2015-07-02 14:43:30 -07:00 |
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Yunsup Lee
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702ddabe26
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add ExampleSmallConfig for README
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2014-10-07 02:07:59 -07:00 |
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Yunsup Lee
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e25d420155
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Improve ChiselConfig composability; bump chisel
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2014-10-06 13:43:40 -07:00 |
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Yunsup Lee
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73eac94a65
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Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
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2014-10-06 13:40:35 -07:00 |
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Henry Cook
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122733b3a9
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file name consistency
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2014-10-06 13:37:38 -07:00 |
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Henry Cook
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0b5f23a209
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Streamlined uncore for release
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2014-10-06 13:37:15 -07:00 |
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Adam Izraelevitz
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15fb4730ec
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Add BuildTile parameter for Tile
Conflicts:
rocket
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2014-09-25 06:50:45 -07:00 |
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Henry Cook
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7398b00d93
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dir supplied by function
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2014-09-25 06:50:41 -07:00 |
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Henry Cook
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5a840c5520
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support for multiple tilelink paramerterizations in same design
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2014-09-25 06:50:30 -07:00 |
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Donggyu Kim
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eb384f6461
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new RocketChipBackend implementation
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2014-09-25 06:47:12 -07:00 |
|
Scott Beamer
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f2ca887de3
|
better fpga configs
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2014-09-25 06:47:03 -07:00 |
|
Donggyu Kim
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4fe48f5a0a
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bump chisel
|
2014-09-25 06:46:58 -07:00 |
|
Donggyu Kim
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60d90f5230
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recover collectNodesIntoComp in Backends.scala
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2014-09-25 06:46:50 -07:00 |
|
Donggyu Kim
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a53091b40f
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remove collectNodesIntoComp from Backends.scala
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2014-09-25 06:46:27 -07:00 |
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Scott Beamer
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f4e6cd75ab
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turn off fpu for default fpga config.
a larger fpga can use defaultconfig
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2014-09-25 06:46:16 -07:00 |
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Yunsup Lee
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09de2e2794
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compute number of outstanding misses for DRAMSideLLCNull
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2014-09-12 18:09:38 -07:00 |
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Yunsup Lee
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1cfd9f5a0e
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add LICENSE
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2014-09-12 10:15:04 -07:00 |
|
Yunsup Lee
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c98afa1fea
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turn off DRAMSideLLC
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2014-09-11 22:10:25 -07:00 |
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Yunsup Lee
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b5a64487eb
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turn off DRAMSideLLC
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2014-09-11 22:07:44 -07:00 |
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Yunsup Lee
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02c08a156f
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generate consts.vh from chisel source
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2014-09-10 17:14:55 -07:00 |
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Yunsup Lee
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6b6bdd2b83
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decommission Slave top-level module for fpga build
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2014-09-08 00:23:15 -07:00 |
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Yunsup Lee
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ddfd3ce968
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further generalize fpga/vlsi builds
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2014-09-08 00:21:57 -07:00 |
|
Henry Cook
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ae05125f29
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Adjustements to top-level parameters and knobs for hwacha
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2014-09-07 17:57:33 -07:00 |
|
Henry Cook
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4126678c9d
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Merge branch 'dse'
Conflicts:
rocket
uncore
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2014-09-06 06:59:14 -07:00 |
|
Henry Cook
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82467313dd
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merge in rocketchip changes from master
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2014-09-02 13:51:57 -07:00 |
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Yunsup Lee
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7734285507
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forgot to comment out hwacha
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2014-09-01 09:01:36 -07:00 |
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Yunsup Lee
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c03c09ec31
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update for rocket-chip release
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2014-08-31 20:26:55 -07:00 |
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Henry Cook
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78ab83d224
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refactor fpga top/config
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2014-08-28 13:07:54 -07:00 |
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Henry Cook
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bf356b9cb4
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Refactor to combine fpga and vlsi tops, part 1
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2014-08-24 19:30:53 -07:00 |
|
Henry Cook
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a41d55b643
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Final parameter refactor.
|
2014-08-23 01:26:03 -07:00 |
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Scott Beamer
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63b62394d9
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added l2 to fpga
with new chisel & uncore, it goes into brams
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2014-08-20 15:41:07 -07:00 |
|
Henry Cook
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1563c1bb36
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Fixed cache params. Asm and bmark tests pass.
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2014-08-12 15:00:54 -07:00 |
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Henry Cook
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7f07771600
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Cache utility traits. Completely compiles, asm tests hang.
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2014-08-11 18:37:10 -07:00 |
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Henry Cook
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1983260e6f
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a few more fixes. some param lookups fail (here() in Alter blocks)
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2014-08-10 23:08:21 -07:00 |
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Henry Cook
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63bd0b9d2a
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Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
|
2014-08-08 12:27:47 -07:00 |
|
Adam Izraelevitz
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08d81d0892
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First cut at using new chisel parameters for toplevel parameters and fpu
|
2014-08-01 18:09:37 -07:00 |
|
Henry Cook
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434da22283
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Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel)
|
2014-05-28 17:16:49 -07:00 |
|
Henry Cook
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b0ccb88982
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make outer cache type choice a top-level const
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2014-05-28 14:46:07 -07:00 |
|
Henry Cook
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ce056b4b89
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client/master -> inner/outer
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2014-04-29 16:50:30 -07:00 |
|
Henry Cook
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224e286dd3
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New uncore config objects. Backends get their own file. Simplify fpga uncore.
|
2014-04-26 19:46:11 -07:00 |
|
Henry Cook
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3d4273954a
|
TileLinkIO.GrantAck -> TileLinkIO.Finish
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2014-04-26 15:19:25 -07:00 |
|
Henry Cook
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fbf6e44376
|
fix connection error in fpga uncore
|
2014-04-24 11:58:59 -07:00 |
|
Henry Cook
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cfd6748318
|
patches to make FAME1/dram IOs compile with up-to-date chisel (bumped)
|
2014-04-21 17:26:33 -07:00 |
|
Henry Cook
|
2cb4dbae39
|
Refactored uncore constants and tilelink data
|
2014-04-10 13:19:50 -07:00 |
|
Henry Cook
|
5a5f69bfca
|
finished uncore constant/tilelink data refactor
|
2014-04-10 13:13:46 -07:00 |
|
Andrew Waterman
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817517c663
|
Better branch prediction
|
2014-04-07 16:08:06 -07:00 |
|
Henry Cook
|
56f515c255
|
first steps in uncore constant/tilelink data refactor
|
2014-03-30 09:21:08 -07:00 |
|
Andrew Waterman
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d055c0ebaf
|
Push rocket/hardfloat/chisel
|
2014-03-04 16:39:06 -08:00 |
|
Yunsup Lee
|
e20d50436a
|
committed in the wrong directory, meant to commit in the hwacha directory
|
2014-03-01 00:01:35 -08:00 |
|
Yunsup Lee
|
8c459df3b6
|
flush deck when xcpt occurs, fixes remaining p test bugs
|
2014-02-28 22:50:34 -08:00 |
|
Stephen Twigg
|
755293d785
|
Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha).
|
2014-02-14 10:12:09 -08:00 |
|
Andrew Waterman
|
11e69a73cd
|
Fix tests when !hwacha; disable hwacha by default
|
2014-02-06 03:08:33 -08:00 |
|
Stephen Twigg
|
8c96e27ca6
|
Merge branch 'master' into hwacha-port
Mostly Stable version that is passing tests
|
2014-02-04 17:20:28 -08:00 |
|
Henry Cook
|
382fa0ef27
|
cleanups supporting uncore hierarchy
|
2014-01-31 16:03:58 -08:00 |
|
Stephen Twigg
|
e7ee94bcc8
|
Merge branch 'master' into hwacha-port
|
2014-01-21 15:23:05 -08:00 |
|
Stephen Twigg
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ee0c4ca291
|
Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations)
|
2014-01-21 14:48:04 -08:00 |
|
Andrew Waterman
|
6f028b2d52
|
Increase BTB size; fix Rocket FPU bug
|
2014-01-17 03:53:08 -08:00 |
|
Andrew Waterman
|
a43cf9d688
|
Update to new privileged ISA
|
2013-11-25 04:45:06 -08:00 |
|
Stephen Twigg
|
e50c5180cd
|
Merge branch 'master' into hwacha
|
2013-11-14 16:03:55 -08:00 |
|
Yunsup Lee
|
1d6d4b4e96
|
move htif to uncore
|
2013-11-07 13:19:19 -08:00 |
|
Yunsup Lee
|
c810847761
|
hookup all memory ports
|
2013-11-05 17:12:25 -08:00 |
|
Stephen Twigg
|
7da65434ee
|
Initial commit for the hwacha reference-chip/rocket re-integration.
|
2013-10-30 20:44:02 -07:00 |
|
Stephen Twigg
|
36dfff5ee8
|
Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy.
|
2013-09-25 01:21:41 -07:00 |
|
Andrew Waterman
|
b7d7ced41b
|
Update to new ISA
|
2013-09-21 06:40:23 -07:00 |
|
Huy Vo
|
09247c0e0b
|
fix to sram init pins
|
2013-09-19 20:12:10 -07:00 |
|
Andrew Waterman
|
80003b3019
|
Support RoCC
|
2013-09-15 04:25:26 -07:00 |
|
Andrew Waterman
|
fbdbb01232
|
update to new isa; disable vector tests
|
2013-09-12 17:04:03 -07:00 |
|
Henry Cook
|
b42e140e05
|
NetworkIOs no longer use thunks
|
2013-09-10 16:23:52 -07:00 |
|
Stephen Twigg
|
6cde69e95d
|
Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.
|
2013-09-09 14:31:18 -07:00 |
|
Yunsup Lee
|
ba9bbc27df
|
apply same change to fpga top-level
|
2013-08-24 15:50:03 -07:00 |
|
Yunsup Lee
|
76cd90fc01
|
parameterize number of SCRs
|
2013-08-24 15:47:42 -07:00 |
|
Yunsup Lee
|
0884bc9789
|
fix DRAMSideLLCNull entries
|
2013-08-24 13:20:38 -07:00 |
|
Yunsup Lee
|
1e3ac0afa9
|
back to NTILES=1
|
2013-08-24 13:10:30 -07:00 |
|
Henry Cook
|
b06d33da2f
|
Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
|
2013-08-19 19:54:41 -07:00 |
|
Henry Cook
|
85e5ce046f
|
pulled submodule commits, uncore sbt standardized
|
2013-08-15 17:07:13 -07:00 |
|
Henry Cook
|
6b20556661
|
Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2
Conflicts:
chisel
riscv-hwacha
riscv-rocket
uncore
|
2013-08-15 16:39:30 -07:00 |
|
Henry Cook
|
784e017bae
|
Final Reg standardization
|
2013-08-15 16:37:58 -07:00 |
|
Henry Cook
|
9b70ecf546
|
Reg standardization
|
2013-08-13 17:53:19 -07:00 |
|
Huy Vo
|
cc6631ae4d
|
reset -> _reset
|
2013-08-12 20:52:55 -07:00 |
|
Henry Cook
|
11e131af47
|
initial attempt at upgrade
|
2013-08-12 10:46:22 -07:00 |
|
Henry Cook
|
199e76fc77
|
Fold uncore constants into TileLinkConfiguration, update coherence API
|
2013-08-02 16:31:27 -07:00 |
|